A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORS

A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORS

Ali Ghorbani1 and Mehdi Sarkhosh1 and Elnaz Fayyazi 1 and Neda Mahmoudi 1 and Peiman Keshavarzian2

1Department of Computer Engineering, Science And Research Branch ,Islamic Azad University,Kerman,Iran

2Department of Computer Engineering, Kerman Branch ,Islamic Azad University,Kerman,Iran

ABSTRACT

Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.

KEYWORDS

Full Adder, Carbon Nano-tube, Carbon Nano-tube field effect transistor, Low power full adder, CNTFET

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics04.pdf

http://airccse.org/journal/vlsi/vol3.html

DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CIRCUIT

DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CIRCUIT

Rajkumar Sarma1 and Veerati Raju2

1School of Electronics Engineering, Lovely Professional University, Punjab (India)

2Department of VLSI, Lovely Professional University, Punjab (India)

ABSTRACT

Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.

KEYWORDS

GDI, PTL, PDP, low power, Full Adder & VLSI.

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics03.pdf

http://airccse.org/journal/vlsi/vol3.html

CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELL

CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELL

Fazel Sharifi1, Amir Momeni1 and keivan Navi1

Department of Electrical and Computer Engineering, Shahid Beheshti University,Tehran, Iran

ABSTRACT

In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).

KEYWORDS

CNFET, MOSFET, Full-Adder cell, Basic gates.

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics02.pdf

http://airccse.org/journal/vlsi/vol3.html

October - International journal of VLSI design & Communication Systems (...

A COMPARATIVE STUDY OF ULTRA-LOW VOLTAGE DIGITAL CIRCUIT DESIGN

A COMPARATIVE STUDY OF ULTRA-LOW VOLTAGE DIGITAL CIRCUIT DESIGN

Aaron Arthurs, Justin Roark, and Jia Di

Computer Engineering and Computer Science Department, University of Arkansas Fayetteville, Arkansas, USA

ABSTRACT

Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which, however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delayinsensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.

KEYWORDS

Ultra-Low Voltage, Asynchronous Logic, Delay-Insensitive, Schmitt-Triggered, Silicon-on-Insulator

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics01.pdf

http://airccse.org/journal/vlsi/vol3.html

UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE

UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE

Lakhan Shiva Kamireddy1 and Lakhan Saiteja K2

1Department of Electrical and Computer Engineering,University of Colorado, Boulder, USA

2Indian Institute of Technology Kharagpur, West Bengal, India

ABSTRACT

The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.

KEYWORDS

Functional Verification, QuestaSim, Reusable VIP, Simulation, SPI Master Core, Universal Verification Methodology (UVM) 

Original Source Link : http://aircconline.com/vlsics/V9N5/9518vlsi02.pdf

http://airccse.org/journal/vlsi/current.html

STATIC NOISE MARGIN OPTIMIZED 11NM SHORTED-GATE AND INDEPENDENT-GATE LOW POWER 6T FINFET SRAM TOPOLOGIES

STATIC NOISE MARGIN OPTIMIZED 11NM SHORTED-GATE AND INDEPENDENT-GATE LOW POWER 6T FINFET SRAM TOPOLOGIES

DustenVernor, Santosh Koppa and Eugene John

Department of Electrical andComputer Engineering, University of Texas at San Antonio, Texas, USA

ABSTRACT

This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a 6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with optimized performance using shorted gate and independent gate low power FinFET models. By optimizing the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters. Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells with minimal impact on the subthreshold leakage currents, performance and energy consumption.

KEYWORDS

SRAM, Leakage Power, Write Delay, Read Delay, FinFET, Static Noise Margin, SNM, Back GateBiasing.

Original Source Link : http://aircconline.com/vlsics/V9N5/9518vlsi01.pdf

http://airccse.org/journal/vlsi/current.html

Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

Subodh Wairya1, Rajendra Kumar Nagaria2 and Sudarshan Tiwari2

1Department of Electronics Engineering, Institute of Engineering & Technology (I.E.T),Lucknow, India, 226021

2Department of ECED, Motilal Nehru National Institute of Technology (MNNIT), Allahabad, India, 211004

ABSTRACT

This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP). 

KEYWORDS

Hybrid full adder, XOR-XNOR circuit, High Speed, Low Power, Very Large Scale Integrated (VLSI)Circuits,  

Original Scource Link : http://aircconline.com/vlsics/V3N2/3212vlsics19.pdf

http://airccse.org/journal/vlsi/vol3.html

Current Issue

Current Issue

October 2018, Volume 9, Number 5

Static Noise Margin Optimized 11nm Shorted-Gate and Independent-Gate Low Power 6T FINFET SRAM Topologies

DustenVernor, Santosh Koppa and Eugene John, University of Texas at San Antonio, USA

http://aircconline.com/vlsics/V9N5/9518vlsi01.pdf

UVM Based Reusable Verification IP for Wishbone Compliant SPI Master Core

Lakhan Shiva Kamireddy1 and Lakhan Saiteja K2, 1University of Colorado, USA and 2Indian Institute of Technology - Kharagpur, India

http://aircconline.com/vlsics/V9N5/9518vlsi02.pdf