PERFORMANCE EVALUATION OF DIFFERENT SRAM CELL STRUCTURES AT DIFFERENT TECHNOLOGIES
Sapna Singh1, Neha Arora2, Meenakshi Suthar3 and Neha Gupta4
Faculty of Engineering Technology, Mody Institute of Technology and Science,Lakshmangarh, Sikar, INDIA
ABSTRACT
In recent years the demand for low power devices has been increases tremendously. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, thus designers are required to choose appropriate techniques that satisfy application and product needs. The demand for static random-access memory (SRAM) is increasing with large use of SRAM in System On-Chip and high-performance VLSI circuits. This paper represents the simulation of different SRAM cells and their comparative analysis on different parameters such as Power Supply Voltage, area efficiency etc to enhance the performance. All the simulations have been carried out on BSIM 3V3 90nm, 45nm and 32 technology at Tanner EDA tool.
KEYWORDS
CMOS Logic, Low power, Speed, SRAM and VLSI.
Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics08.pdf
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