DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHNOLOGY
Rajendra Prasad S1, Prof. B K Madhavi2 and Prof. K Lal Kishore3
1Department of ECE, ACE Engineering College, Hyderabad, AP, India.
2Department of ECE, GCET, Keesara, Hyderabad, AP, India.
3Department of ECE, JNT University, Hyderabad, AP, India.
ABSTRACT
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
KEYWORDS
SRAM Cell, CNTFET, 32nm Technology, HSPICE, Low-Power
Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics14.pdf
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