LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITS

LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITS

M. Janaki Rani1 and S. Malarkann2

1 Research Scholar, Sathyabama University, Chennai -119, Tamilnadu

2 Principal, Manakula Vinayagar Institute of Technology, Puducherry

ABSTRACT

A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

KEYWORDS

Leakage Power, Pass Transistors, Process Technology, Stacking Effect, Transmission Gates

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics02.pdf

http://airccse.org/journal/vlsi/vol3.html