LOW POWER FOLDED CASCODE OTA

LOW POWER FOLDED CASCODE OTA

Swati Kundra1, Priyanka Soni2 and Anshul Kundra3

1,2FET, Mody Institute of Technology & Science, Lakshmangarh, Sikar-322331, INDIA

3Departmaent of E.C.E, Ambedkar Institute of Technology, New Delhi-110031, INDIA

ABSTRACT

Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.

Keywords

Folded Cascode OTA, Self Cascode, Stacking Technique

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics11.pdf

http://airccse.org/journal/vlsi/vol3.html

SYSTEM ON PROGRAMMABLE CHIP FOR PERFOMANCE ESTIMATION OF LOOM MACHINE

SYSTEM ON PROGRAMMABLE CHIP FOR PERFOMANCE ESTIMATION OF LOOM MACHINE

Gurpreet Singh1, Ajay Kumar Roy2, Surekha K S3, S Pujari4

1Infosys, Chandigarh, India

2 Infosys, Hyderabad, India

3Army Institute of Technology, Dighi, Pune, India

4 SUIIT, Sambalpur University, sambalpur, Odisha, India

ABSTRACT

System on programmable chip for the performance estimation of loom machine, which calculates the efficiency and meter count for weaved cloth automatically. Also it calculates the efficiency of loom machine. Previously the same was done using manual process which was not efficient. This article is intended for loom machines which are not modern.

KEYWORDS

Loom machine, efficiency, meter count 

Original source Link : http://aircconline.com/vlsics/V3N1/3112vlsics10.pdf

http://airccse.org/journal/vlsi/vol3.html

Dual Metal Gate and Conventional MOSFET at Sub nm for Analog Application

Dual Metal Gate and Conventional MOSFET at Sub nm for Analog Application

Sonal Aggarwal1 and Rajbir Singh2

1Department of Electronic Science, Kurukshetra university,Kurukshetra

2Department of Electronic Science,Kurukshetra University, Kurukshetra

Abstract.

The use of nanometer CMOS technologies (below 90nm) however brings along significant challenges for circuit design (both analog and digital). By reducing the dimensions of transistors many physical phenomenon like gate leakage, drain induced barrier lowering and many more effects comes into picture. Reducing the feature size in the technology of device with the addition of ever more interconnect layers, the density of the digital as well as analog circuit will increase while intrinsic gate switching delay is reduced . We have simulated conventional and DMG MOSFET at 30nm scale using Silvaco TAD tool and obtained result. A two dimensional device simulation was carried out and observed that DMG MOSFET has a low leakage current as compared to conventional MOSFET and find suitable application in analog circuits.

Keywords

Gate leakage, DMG MOSFET, Silvaco TCAD tool, work function, trans-conductance, gain, Moore’s Law. 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics09.pdf

http://airccse.org/journal/vlsi/vol3.html

International Journal of VLSI design & Communication Systems ( VLSICS )

International Journal of VLSI design & Communication Systems ( VLSICS )

http://airccse.org/journal/vlsi/vlsics.html

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

                            

Scope & Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include, but are not limited to, the following:

    * Design

    * VLSI Circuits

    * Computer-Aided Design (CAD)

    * Low Power and Power Aware Design

    * Testing, Reliability, Fault-Tolerance

    * Emerging Technologies

    * Post-CMOS VLSI

    * VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

    * Nano Electronics, Molecular, Biological and Quantum Computing

    * Intellectual Property Creating and Sharing

    * Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through E-mail; vlsicsjournal@airccse.org.  Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates:

·         Submission Deadline    :  September 08, 2018

·         Acceptance Notification :  October 08, 2018

·         Final Manuscript Due     :  October 16, 2018

·         Publication Date : Determined by the Editor-in-Chief

For other details please visit: http://airccse.org/journal/vlsi/vlsics.html

PERFORMANCE EVALUATION OF DIFFERENT SRAM CELL STRUCTURES AT DIFFERENT TECHNOLOGIES

PERFORMANCE EVALUATION OF DIFFERENT SRAM CELL STRUCTURES AT DIFFERENT TECHNOLOGIES

Sapna Singh1, Neha Arora2, Meenakshi Suthar3 and Neha Gupta4

Faculty of Engineering Technology, Mody Institute of Technology and Science,Lakshmangarh, Sikar, INDIA

ABSTRACT

In recent years the demand for low power devices has been increases tremendously. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, thus designers are required to choose appropriate techniques that satisfy application and product needs. The demand for static random-access memory (SRAM) is increasing with large use of SRAM in System On-Chip and high-performance VLSI circuits. This paper represents the simulation of different SRAM cells and their comparative analysis on different parameters such as Power Supply Voltage, area efficiency etc to enhance the performance. All the simulations have been carried out on BSIM 3V3 90nm, 45nm and 32 technology at Tanner EDA tool.

KEYWORDS

CMOS Logic, Low power, Speed, SRAM and VLSI. 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics08.pdf

http://airccse.org/journal/vlsi/vol3.html

High Speed, Low Power Current Comparators with Hysteresis

High Speed, Low Power Current Comparators with Hysteresis

Neeraj K. Chasta

Dhirubhai Ambani Institute of Iinformation & Communication Technology, Gandhinagar,Gujarat

ABSTRACT

This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis), where comparator gives high accuracy (less than 50nA) and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180nm CMOS process technology for a supply voltage of 3V.

KEYWORDS

Current Mode, Current Comparator, Hysteresis.

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics07.pdf

http://airccse.org/journal/vlsi/vol3.html

DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGY

DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGY

Naagesh. S. Bhat1

1Developer, Mahindra Satyam Ltd., Bangalore, India

ABSTRACT

Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.

KEYWORDS

Carbon nanotube field-effect transistor (CNTFET), Static RAM (SRAM), HSPICE 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics06.pdf

http://airccse.org/journal/vlsi/vol3.html

Giga bit per second Differential Scheme for High Speed Interconnect

Giga bit per second Differential Scheme for High Speed Interconnect

Mandeep Singh Narula*, Pankaj Rakheja*, Charu Rana*

*ITM University, School of Engineering & Tech, Dept. of EECE, Gurgaon (Haryana),India

Abstract : 

The performance of many digital systems today is limited by the interconnection bandwidth between chips. Although the processing performance of a single chip has increased dramatically since the inception of the integrated circuit technology, the communication bandwidth between chips has not enjoyed as much benefit. Most CMOS chips, when communicating off-chip, drive unterminated lines with full-swing CMOS drivers. Such full-swing CMOS interconnect ring-up the line, and hence has a bandwidth that is limited by the length of the line rather than the performance of the semiconductor technology. Thus, as VLSI technology scales, the pin bandwidth does not improve with the technology, but rather remains limited by board and cable geometry, making off-chip bandwidth an even more critical bottleneck. In order to increase the I/O Bandwidth, some efficient high speed signaling standard must be used which considers the line termination, signal integrity, power dissipation, noise immunity etc  In this work, a transmitter has been developed for high speed offchip communication. It consists of low speed input buffer, serializer which converts parallel input data into serial data and a current mode driver which converts the voltage mode input signals into current over the transmission line. Output of 32 low speed input buffers is fed to two serializer, each serializer converting 16 bit parallel data into serial data stream. Output of two serializers is fed to LVDS current mode driver. The serial link technique used in this work is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the receiver end. Serial link is the design of choice in any application where the cost of the communication channel is high and duplicating the links in large numbers is uneconomical. 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics04.pdf

http://airccse.org/journal/vlsi/vol3.html

SELF CORRECTING MEMORY DESIGN FOR FAULT FREE CODING IN PROGRESSIVE DATA STREAMING APPLICATION

SELF CORRECTING MEMORY DESIGN FOR FAULT FREE CODING IN PROGRESSIVE DATA STREAMING APPLICATION

Harikishore.Kakarla1, Madhavi Latha.M2 and Habibulla Khan3

1, 3Department of ECE, KL University, Guntur, Andhra Pradesh, India.

2Department of ECE, JNTUH, Hyderabad, Andhra Pradesh, India

ABSTRACT

Fault diagnosis in processing digital system application has raised various limiting problems. While basic objective of fault tolerant systems is to minimize the fault occurring in the device, the processing error is an additional error to be considered. Past approaches were observed to be focusing much on internal fault in digital device, the error due to processing and communication is to be developed. In this paper a self correcting approach to memory design based on memory interface is proposed. The error approach observed in case of forwarding binary data to encode, store and retrieve with error free coding is proposed. The Process of memory error free coding results in higher reliability in case of bit and block coding.

KEYWORDS

Memory fault, progressive coding, memory section addressing, bit/block errors. 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics03.pdf

http://airccse.org/journal/vlsi/vol3.html

LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITS

LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITS

M. Janaki Rani1 and S. Malarkann2

1 Research Scholar, Sathyabama University, Chennai -119, Tamilnadu

2 Principal, Manakula Vinayagar Institute of Technology, Puducherry

ABSTRACT

A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

KEYWORDS

Leakage Power, Pass Transistors, Process Technology, Stacking Effect, Transmission Gates

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics02.pdf

http://airccse.org/journal/vlsi/vol3.html

An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance

An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance

Brinda Bhowmick and Srimanta Baishya

1Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Silchar, India

ABSTRACT

In this paper fringe capacitance of double hetero gate Tunnel FET has been studied. The physical model for fringe capacitance is derived considering source gate overlap and gate drain non overlap. Inerface trap charge and oxide charges are also introduced under positive bias stress and hot carrier stress and their effect on fringe capacitance is also studied. The fringe capacitance is significant speed limiter in Double gate technology. The model is tested by comparing with simulation results obtained from Sentauras TCAD simulations.

KEYWORDS

Band-to-band tunnelling, hetero-gate, parasitic fringe capacitance. 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics01.pdf

http://airccse.org/journal/vlsi/vol3.html

Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Utilization

Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Utilization

Bhavana Pote1,V. N. Nitnaware2,and Dr. S. S. Limaye3

1Department of Electronics, Ramdeobaba Kamla Nehru College of Engg, Nagpur, India

2Department of EDT, Ramdeobaba Kamla Nehru College of Engg, Nagpur, India

3Jhulelal Institute of Technology, Nagpur, India 

Abstract:

With the shrinking technology, reduced scale and power-hungry chip IO leads to System on Chip. The design of SOC using traditional standard bus scheme encounters with issues like non-uniform delay and routing problems. Crossbars could scale better when compared to buses but tend to become huge with increasing number of nodes. NOC has become the design paradigm for SOC design for its highly regularized interconnect structure, good scalability and linear design effort. The main components of an NoC topology are the network adapters, routing nodes, and network interconnect links. This paper mainly deals with the implementation of full custom SRAM based arrays over D FF based register arrays in the design of input module of routing node in 2D mesh NOC topology. The custom SRAM blocks replace D FF(D flip flop) memory implementations to optimize area and power of the input block. Full custom design of SRAMs has been carried out by MILKYWAY, while physical implementation of the input module with SRAMs has been carried out by IC Compiler of SYNOPSYS.The improved design occupies approximately  30% of the area of the original design. This is in conformity to the ratio of the area of an SRAM cell to the area of a D flip flop, which is approximately 6:28.The power consumption is almost halved to 1.5 mW. Maximum operating frequency is improved from 50 MHz to 200 MHz. It is intended to study and quantify the behavior of the single packet array design in relation to the multiple packet array design. Intuitively, a common packet buffer would result in better utilization of available buffer space. This in turn would translate into lower delays in transmission. A MATLAB model is used to show quantitatively how performance is improved in a common packet array design.

Keywords : 

2D mesh, virtual output queuing, HOL blocking, FIFO, DDC file, GDS format. 

Original Source Link: http://aircconline.com/vlsics/V2N4/2411vlsics15.pdf

http://airccse.org/journal/vlsi/vol2.html

DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHNOLOGY

DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHNOLOGY

Rajendra Prasad S1, Prof. B K Madhavi2 and Prof. K Lal Kishore3

1Department of ECE, ACE Engineering College, Hyderabad, AP, India.

2Department of ECE, GCET, Keesara, Hyderabad, AP, India.

3Department of ECE, JNT University, Hyderabad, AP, India.

ABSTRACT

The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%. 

KEYWORDS

SRAM Cell, CNTFET, 32nm Technology, HSPICE, Low-Power

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics14.pdf

http://airccse.org/journal/vlsi/vol2.html

A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs

A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs

Ramya Menon C. and Vinod Pangracious

Department of Electronics & Communication Engineering, Rajagiri School of Engineering & Technology, Kochi, Kerala

ABSTRACT

In a multiprocessor system on chip (MPSoC) IC the processor is one of the highest heat dissipating devices. The temperature generated in an IC may vary with floor plan of the chip. This paper proposes an integration and thermal analysis methodology to extract the peak temperature and temperature distribution of 2-dimensional and 3-dimensional multiprocessor system-on-chip. As we know the peak temperature of chip increases in 3-dimensional structures compared to 2-dimensional ones due to the reduced space in intra-layer and inter-layer components. In sub-nanometre scale technologies, it is inevitable to analysis the heat developed in individual chip to extract the temperature distribution of the entire chip. With the technology scaling in new generation ICs more and more components are integrated to a smaller area. Along with the other parameters threshold voltage is also scaled down which results in exponential increase in leakage current. This has resulted in rise in hotspot temperature value due to increase in leakage power. In this paper, we have analysed the temperature developed in an IC with four identical processors at 2.4 GHz in different floorplans. The analysis has been done for both 2D and 3D arrangements. In the 3D arrangement, a three layered structure has been considered with two Silicon layers and a thermal interface material (TIM) in between them. Based on experimental results the paper proposes a methodology to reduce the peak temperature developed in 2D and 3D integrated circuits .

KEYWORDS

Hotspot, Peak Temperature, Three Dimensional Integration, Through silicon Via.

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics13.pdf

http://airccse.org/journal/vlsi/vol2.html

Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed SRAM Cell and DRAM Cell

Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed SRAM Cell and DRAM Cell  

Mr.Viplav A. Soliv1 Dr. Ajay A. Gurjar2

1Department of Electronics and Telecommunication Sipna’s college of Engineering & Technology, Amravati.

2Department of Electronics and Telecommunication Sipna’s college of Engineering & Technology, Amravati.

ABSTRACT

This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) cell and Dynamic Random Access Memory (DRAM) cell to develop low power consumption. SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 12-transistor SRAM cell built from a simple static latch and tri state inverter. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines.

KEYWORDS

Keywords SRAM, DRAM, Low power, 12-T SRAM cell

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics12.pdf

http://airccse.org/journal/vlsi/vol2.html

LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTA

LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTA

Neha Gupta1, Sapna Singh2, Meenakshi Suthar3 and Priyanka Soni4

Faculty of Engineering Technology, Mody Institute of Technology and Science, Lakshmangarh, Sikar, India

ABSTRACT

The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.

KEYWORDS

Bulk-driven MOS, OTA, BOTA, Body effect

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics11.pdf

http://airccse.org/journal/vlsi/vol2.html