HIGH FIN WIDTH MOSFET USING GAA STRUCTURE

HIGH FIN WIDTH MOSFET USING GAA STRUCTURE

S.L.Tripathi1, Ramanuj Mishra2, R.A.Mishra3

Department of Electronics and Communication Engineering, MNNIT, Allahabad

ABSTRACT

This paper describes the design and optimization of gate-all-around (GAA) MOSFETs structures. The optimum value of Fin width and Fin height are investigated for superior subthreshold behavior. Also the performance of Fin shaped GAA with gate oxide HfO2 are simulated and compared with conventional gate oxide SiO2 for the same structure. As a result, it was observed that the GAA with high K dielectric gate oxide has more possibility to optimize the Fin width with improved performance. All the simulations are performed on 3-D TCAD device simulator.

KEYWORDS

Gate all around(GAA),TG FinFET, High K gate oxide, Silicon-On-Insulator(SOI), Work function, Short channel effect, DIBL, Subthreshold Slope,3-D Sentaurus TCAD tool. 

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics09.pdf

http://airccse.org/journal/vlsi/vol3.html

DESIGN AND IMPLEMENTATION OF ANALOG MULTIPLIER WITH IMPROVED LINEARITY 

Nandini A.S1, Sowmya Madhavan2 and Dr Chirag Sharma3

1Department of Electronics and Communication Engineering, Nitte Meenakshi Institute of Technology, Yelahanka, Bangalore- 560064

2Department of Electronics and Communication Engineering, Nitte Meenakshi Institute of Technology, Yelahanka, Bangalore- 560064

3Department of Electronics and Communication Engineering, Nitte Meenakshi Institute of Technology, Yelahanka, Bangalore- 560064

ABSTRACT

Analog multipliers are used for frequency conversion and are critical components in modern radio frequency (RF) systems. RF systems must process analog signals with a wide dynamic range at high frequencies. A mixer converts RF power at one frequency into power at another frequency to make signal processing easier and also inexpensive. A fundamental reason for frequency conversion is to allow amplification of the received signal at a frequency other than the RF, or the audio, frequency. This paper deals with two such multipliers using MOSFETs which can be used in communication systems. They were designed and implemented using 0.5 micron CMOS process. The two multipliers were characterized for power consumption, linearity, noise and harmonic distortion. The initial circuit simulated is a basic Gilbert cell whose gain is fairly high but shows more power consumption and high total harmonic distortion. Our paper aims in reducing both power consumption and total harmonic distortion. The second multiplier is a new architecture that consumes 43.07 percent less power and shows 22.69 percent less total harmonic distortion when compared to the basic Gilbert cell. The common centroid layouts of both the circuits have also been developed.

KEYWORDS

Multiplier, Gilbert cell, Noise spectral density, Total Harmonic Distortion, Transconductance 

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics08.pdf

http://airccse.org/journal/vlsi/vol3.html

A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONS

1Angila Rose Daniel and 2B. Deepa

1M.Tech in VLSI and embedded systems, Kerala technical university, India

2Assistant professor, EC Department, Kerala technical university, India

ABSTRACT

In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to around the operands to the closest exponent of 2. This way the machine intensive a part of the multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is evaluated by comparing its performance with those of some approximate and correct multipliers using different design parameters. In this proposed approach combined the conventional RoBA multiplier with Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the DSP.

KEYWORDS

Accuracy, approximate computing, efficient, error analysis, high speed multiplier, RoBa architecture, kogge stone adder, DSP processing

Orignal Source Link : http://aircconline.com/vlsics/V10N1/10119vlsi01.pdf

http://airccse.org/journal/vlsi/vol10.html

IMPACT OF DEVICE PARAMETERS OF TRIPLE GATE SOI-FINFET ON THE PERFORMANCE OF CMOS INVERTER AT 22NM

Prathima. A1, Kiran Bailey 2 , K.S.Gurumurthy 3

1, 2 Department of Electronics and Communication Engineering, BMSCE, Bangalore

3Department of ECE, UVCE, Bangalore University, Bangalore

ABSTRACT

A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the downscaling of the gate oxide thickness due to higher gate leakage current and gate capacitance.

KEYWORDS

DIBL, Process and Device simulation, SCEs, SOI FinFETs, Sub threshold Slope, TCAD 

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics07.pdf

http://airccse.org/journal/vlsi/vol3.html

MODELING OF BUILT-IN POTENTIAL VARIATIONS OF CYLINDRICAL SURROUNDING GATE (CSG) MOSFETS

MODELING OF BUILT-IN POTENTIAL VARIATIONS OF CYLINDRICAL SURROUNDING GATE (CSG) MOSFETS

Santosh Kumar Gupta1 and S. Baishya2

Department of Electronics & Communication Engineering, National Institute of Technology Silchar, Assam – 788 010, INDIA

ABSTRACT

Due to aggressive scaling of MOSFETs the parasitic fringing field plays a major role in deciding its characteristics. These fringing fields are now not negligible and should be taken into account for deriving the MOSFET models. Due to this fringing field effect there are some charges induced in the source/drain extension regions which will change the potential barrier at the source-channel from its theoretical nominal values. In this paper an attempt has been made to model variation of built-in potential variation for a cylindrical surrounding gate MOSFET. The model has been verified to be working in good agreement with the variations of gate length and channel radius.

KEYWORDS

Barrier lowering, cylindrical surround gate (CSG) MOSFET, fringing field, short channel effects (SCEs) 

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics06.pdf

http://airccse.org/journal/vlsi/vol3.html

LOW POWER DYNAMIC BUFFER CIRCUITS

LOW POWER DYNAMIC BUFFER CIRCUITS

Amit Kumar Pandey, Ram Awadh Mishra and Rajendra Kumar Nagaria

Department of Electronics and Communication, M.N.N.I.T, Allahabad, India

ABSTRACT

In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant  switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18µm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing standard domino circuit for different logic function, loading condition, clock frequency, temperature and power supply. Our proposed circuits reduce power consumption and power delay product as compared to standard domino circuit.

KEYWORDS

Buffer, Dynamic circuit, Power consumption, Delay, Precharge pulse. 

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics05.pdf

http://airccse.org/journal/vlsi/vol3.html

DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme

DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme

Majed ValadBeigi, Farshad Safaei and Bahareh Pourshirazi

Department of Electrical and Computer Engineering, Shahid Beheshti University G.C, Evin 1983963113, Tehran, IRAN

ABSTRACT

Dynamic network reconfiguration is described as the process of replacing one routing function with another while the network keeps running. The main challenge is avoiding deadlock anomalies while keeping limitations on message injection and forwarding minimal. Current approaches, whose complexity is so high that their practical applicability is limited, either require the existence of extra network resources like virtual channels, or they affect the performance of the network during the reconfiguration process. In this paper we present a simple, fast and efficient mechanism for dynamic network reconfiguration which is based on regressive deadlock recoveries instead of avoiding deadlocks. The mechanism which is referred to as DBR guarantees a deadlock-free reconfiguration based on wormhole switching (WS) and it does not require additional resources. In this approach, the need for a reliable message transmission has led to a modified WS mechanism which includes additional flits or control signals. DBR allows cycles to be formed and in such conditions when a deadlock occurs, the messages suffer from time-out. Then, this method releases the buffers and channels from the current node and thus the source retransmits the message after a random time gap. Evaluating results reveal that the mechanism shows substantial performance improvements over the other methods and it works efficiently in different topologies with various routing algorithms. 

KEYWORDS

Interconnection Networks; Dynamic Reconfiguration; Deadlock Recovery; Fault-Tolerance

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics02.pdf

http://airccse.org/journal/vlsi/vol3.html