LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITS

LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITS

M. Janaki Rani1 and S. Malarkann2

1 Research Scholar, Sathyabama University, Chennai -119, Tamilnadu

2 Principal, Manakula Vinayagar Institute of Technology, Puducherry

ABSTRACT

A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.

KEYWORDS

Leakage Power, Pass Transistors, Process Technology, Stacking Effect, Transmission Gates

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics02.pdf

http://airccse.org/journal/vlsi/vol3.html

An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance

An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance

Brinda Bhowmick and Srimanta Baishya

1Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Silchar, India

ABSTRACT

In this paper fringe capacitance of double hetero gate Tunnel FET has been studied. The physical model for fringe capacitance is derived considering source gate overlap and gate drain non overlap. Inerface trap charge and oxide charges are also introduced under positive bias stress and hot carrier stress and their effect on fringe capacitance is also studied. The fringe capacitance is significant speed limiter in Double gate technology. The model is tested by comparing with simulation results obtained from Sentauras TCAD simulations.

KEYWORDS

Band-to-band tunnelling, hetero-gate, parasitic fringe capacitance. 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics01.pdf

http://airccse.org/journal/vlsi/vol3.html

Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Utilization

Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Utilization

Bhavana Pote1,V. N. Nitnaware2,and Dr. S. S. Limaye3

1Department of Electronics, Ramdeobaba Kamla Nehru College of Engg, Nagpur, India

2Department of EDT, Ramdeobaba Kamla Nehru College of Engg, Nagpur, India

3Jhulelal Institute of Technology, Nagpur, India 

Abstract:

With the shrinking technology, reduced scale and power-hungry chip IO leads to System on Chip. The design of SOC using traditional standard bus scheme encounters with issues like non-uniform delay and routing problems. Crossbars could scale better when compared to buses but tend to become huge with increasing number of nodes. NOC has become the design paradigm for SOC design for its highly regularized interconnect structure, good scalability and linear design effort. The main components of an NoC topology are the network adapters, routing nodes, and network interconnect links. This paper mainly deals with the implementation of full custom SRAM based arrays over D FF based register arrays in the design of input module of routing node in 2D mesh NOC topology. The custom SRAM blocks replace D FF(D flip flop) memory implementations to optimize area and power of the input block. Full custom design of SRAMs has been carried out by MILKYWAY, while physical implementation of the input module with SRAMs has been carried out by IC Compiler of SYNOPSYS.The improved design occupies approximately  30% of the area of the original design. This is in conformity to the ratio of the area of an SRAM cell to the area of a D flip flop, which is approximately 6:28.The power consumption is almost halved to 1.5 mW. Maximum operating frequency is improved from 50 MHz to 200 MHz. It is intended to study and quantify the behavior of the single packet array design in relation to the multiple packet array design. Intuitively, a common packet buffer would result in better utilization of available buffer space. This in turn would translate into lower delays in transmission. A MATLAB model is used to show quantitatively how performance is improved in a common packet array design.

Keywords : 

2D mesh, virtual output queuing, HOL blocking, FIFO, DDC file, GDS format. 

Original Source Link: http://aircconline.com/vlsics/V2N4/2411vlsics15.pdf

http://airccse.org/journal/vlsi/vol2.html

DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHNOLOGY

DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHNOLOGY

Rajendra Prasad S1, Prof. B K Madhavi2 and Prof. K Lal Kishore3

1Department of ECE, ACE Engineering College, Hyderabad, AP, India.

2Department of ECE, GCET, Keesara, Hyderabad, AP, India.

3Department of ECE, JNT University, Hyderabad, AP, India.

ABSTRACT

The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%. 

KEYWORDS

SRAM Cell, CNTFET, 32nm Technology, HSPICE, Low-Power

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics14.pdf

http://airccse.org/journal/vlsi/vol2.html

A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs

A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs

Ramya Menon C. and Vinod Pangracious

Department of Electronics & Communication Engineering, Rajagiri School of Engineering & Technology, Kochi, Kerala

ABSTRACT

In a multiprocessor system on chip (MPSoC) IC the processor is one of the highest heat dissipating devices. The temperature generated in an IC may vary with floor plan of the chip. This paper proposes an integration and thermal analysis methodology to extract the peak temperature and temperature distribution of 2-dimensional and 3-dimensional multiprocessor system-on-chip. As we know the peak temperature of chip increases in 3-dimensional structures compared to 2-dimensional ones due to the reduced space in intra-layer and inter-layer components. In sub-nanometre scale technologies, it is inevitable to analysis the heat developed in individual chip to extract the temperature distribution of the entire chip. With the technology scaling in new generation ICs more and more components are integrated to a smaller area. Along with the other parameters threshold voltage is also scaled down which results in exponential increase in leakage current. This has resulted in rise in hotspot temperature value due to increase in leakage power. In this paper, we have analysed the temperature developed in an IC with four identical processors at 2.4 GHz in different floorplans. The analysis has been done for both 2D and 3D arrangements. In the 3D arrangement, a three layered structure has been considered with two Silicon layers and a thermal interface material (TIM) in between them. Based on experimental results the paper proposes a methodology to reduce the peak temperature developed in 2D and 3D integrated circuits .

KEYWORDS

Hotspot, Peak Temperature, Three Dimensional Integration, Through silicon Via.

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics13.pdf

http://airccse.org/journal/vlsi/vol2.html

Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed SRAM Cell and DRAM Cell

Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed SRAM Cell and DRAM Cell  

Mr.Viplav A. Soliv1 Dr. Ajay A. Gurjar2

1Department of Electronics and Telecommunication Sipna’s college of Engineering & Technology, Amravati.

2Department of Electronics and Telecommunication Sipna’s college of Engineering & Technology, Amravati.

ABSTRACT

This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) cell and Dynamic Random Access Memory (DRAM) cell to develop low power consumption. SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 12-transistor SRAM cell built from a simple static latch and tri state inverter. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines.

KEYWORDS

Keywords SRAM, DRAM, Low power, 12-T SRAM cell

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics12.pdf

http://airccse.org/journal/vlsi/vol2.html

LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTA

LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTA

Neha Gupta1, Sapna Singh2, Meenakshi Suthar3 and Priyanka Soni4

Faculty of Engineering Technology, Mody Institute of Technology and Science, Lakshmangarh, Sikar, India

ABSTRACT

The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.

KEYWORDS

Bulk-driven MOS, OTA, BOTA, Body effect

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics11.pdf

http://airccse.org/journal/vlsi/vol2.html