Low Power Reversible Parallel Binary Adder/Subtractor

 Call For Papers..!!!

International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print) 

Webpage URL: http://airccse.org/journal/vlsi/vlsics.html

Low Power Reversible Parallel Binary Adder/Subtractor 

Rangaraju H G1, Venugopal U2, Muralidhara K N3, Raja K B 2

Keywords

Reversible Logic, Garbage Input/output, Quantum Cost, Low Power, Reversible Parallel Binary

Adder/Subtractor.  

Article full text : https://aircconline.com/vlsics/V1N3/0910vlsics03.pdf

Volume URL : https://airccse.org/journal/vlsi/vol1.html

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