Subhra Dhar1, Manisha Pattanaik1, P. Rajaram2,1ABV-Indian Institute of Information Technology and Management, India and 2Jiwaji University, India
ABSTRACT
To manage the increasing static leakage in low power applications, solutions for leakage reduction are sought at the device design and process technology levels. In this paper, 90nm, 70nm and 50 nm groovedgate nMOS devices are simulated using Silvaco device simulator. By changing the corner angle and adjusting few structural parameters, static leakage reduction is achieved in grooved nMOSFETS in ultralow power applications. The simulation results show that leakage contributing currents like the subthreshold current, punchthrough current and tunneling leakage current are reduced. The oxide thickness can be increased without increase in the gate induced drain leakage current, and ON-OFF current ratio is improved and maintained constant even in the deep submicron region. This study can be helpful for low power applications as the static leakage is reduced drastically, as well as be applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this work.
KEYWORDS
Planar MOSFET, Grooved MOSFET, Concave corner, Corner angle, Deep Submicron regime, DIBL
Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics05.pdf
https://airccse.org/journal/vlsi/vol2.html
