International journal of VLSI design & Communication Systems (VLSICS)

International journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527 (print)

Webpage URL: https://airccse.org/journal/vlsi/vlsics.html

Survey on Power Optimization Techniques for Low PowerVLSI Circuitsin Deep Submicron Technology

T. Suguna and M. Janaki Rani, Dr.M.G. R Educational and Research Institute, India

Abstract

CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.

Keywords

leakage power, low power, voltage scaling, power gating, transistor stacking, adiabatic logic

Original Source URL: https://aircconline.com/vlsics/V9N1/9118vlsi01.pdf

Volume URL: https://airccse.org/journal/vlsi/vol9.html

Power Comparison of CMOS and Adiabatic Full Adder Circuits

Y. Sunil Gavaskar Reddy and V. V. G. S. Rajendra Prasad, JNT University, India

ABSTRACT

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.

KEYWORDS

Low-power, adiabatic logic, Full adder, CMOS, Pass transistor logic, Positive feed back adiabatic logic, Transmission gate logic, SERF adder

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics06.pdf

https://airccse.org/journal/vlsi/vol2.html