LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOP

Anurag^#1, Gurmohan Singh^#2, V. Sulochana^#3

^# Centre for Development of Advanced Computing, Mohali, India

ABSTRACT

This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and proposed DETFF are presented and compared at same simulation conditions. The post layout experimental results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84% when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%, 33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed DETFF design is suitable for low power and small area applications.

KEYWORDS

Dual-Edge Triggered, Flip-Flop, High Speed, Low Power, Static D Flip-Flop

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics03.pdf

http://airccse.org/journal/vlsi/vol4.html