HARDWARE EFFICIENT SCALING FREE VECTORING AND ROTATIONAL CORDIC FOR DSP APPLICATIONS

Anita Jain¹ and Kavita Khare²

Department of Electronics and Communication Engineering, MANIT, Bhopal, India

ABSTRACT

The COordinate Rotation DIgital Computer CORDIC algorithm has proved its versatility in computing various transcendental functions by only using the shift and adds operations. This paper presents a new hardware efficient scaling free CORDIC algorithm to operate in vectoring and in rotation mode. The micro rotation of the vector is always in one direction with no scale factor correction. The Range of Convergence RoC is from 0 to 2π. No pre and post processing circuitry is required. 16 bit Scaling free CORDIC Pipelined architecture based on the proposed algorithm is synthesized on FPGA Xilinx VirtexII P device coded in Verilog. Synthesized results show totally scaling free performance with very small dynamic power consumption of .06 mW and maximum delay of 4.123 ns and 9.925 ns in the rotational and vectoring modes respectively. The minimum BEP of the proposed algorithm implementation is 12. Proposed algorithm is faster and efficient in terms of area and accuracy as compared to conventional CORDIC.

KEYWORDS

DSP, Scale Free CORDIC, Systolic array, rotation mode, vectoring mode, RoC, pipeline architecture.

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics02.pdf

http://airccse.org/journal/vlsi/vol4.html