CROSSTALK MINIMIZATION FOR COUPLED RLC INTERCONNECTS USING BIDIRECTIONAL BUFFER AND SHIELD INSERTION

Damanpreet Kaur and V.Sulochana

Centre for Development of Advanced Computing (C-DAC) Mohali, India

ABSTRACT

Crosstalk noise is often induced in long interconnects running parallel to each other. There is a need to minimize the effect of these crosstalk noise so as to maintain the signal integrity in interconnects. In this paper crosstalk noise is minimized using various techniques such as repeater (bidirectional buffer) insertion along with shielding, skewing and shielding & skewing simultaneously. With the help of these techniques crosstalk noise is controlled to a great extent in long interconnects. Pre-layout and Post-layout simulations for crosstalk are carried out for these techniques at 180nm technology node using Cadence EDA tools. The influences of these techniques are analyzed and it is found that crosstalk is reduced up to 32 % with repeater insertion, 47% with skewing, 58% with shielding and 81% with skewing & shielding simultaneously.

KEYWORDS

Crosstalk, Bidirectional Buffer, Shielding, Skewing.

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics04.pdf

http://airccse.org/journal/vlsi/vol4.html

International Journal of VLSI design & Communication Systems( VLSICS )

http://airccse.org/journal/vlsi/vlsics.html

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

Scope & Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include, but are not limited to, the following:

* Design

* VLSI Circuits

* Computer-Aided Design (CAD)

* Low Power and Power Aware Design

* Testing, Reliability, Fault-Tolerance

* Emerging Technologies

* Post-CMOS VLSI

* VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

* Nano Electronics, Molecular, Biological and Quantum Computing

* Intellectual Property Creating and Sharing

* Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through E-mail; vlsicsjournal@airccse.org.  Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates:

·         Submission Deadline    : June 29, 2019

·         Acceptance Notification :  July 29, 2019

·         Final Manuscript Due     :  August 08, 2019

·         Publication Date : Determined by the Editor-in-Chief

For other details please visit: http://airccse.org/journal/vlsi/vlsics.html

LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOP

Anurag^#1, Gurmohan Singh^#2, V. Sulochana^#3

^# Centre for Development of Advanced Computing, Mohali, India

ABSTRACT

This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and proposed DETFF are presented and compared at same simulation conditions. The post layout experimental results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84% when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%, 33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed DETFF design is suitable for low power and small area applications.

KEYWORDS

Dual-Edge Triggered, Flip-Flop, High Speed, Low Power, Static D Flip-Flop

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics03.pdf

http://airccse.org/journal/vlsi/vol4.html

Advances in Materials Science and Engineering: An International Journal  (MSEJ)

ISSN: 2394 - 0824

http://airccse.com/msej/index.html

Call for papers  

Advances in Materials Science and Engineering: An International Journal (MSEJ) is a quarterly open access peer-reviewed journal that publishes articles which contribute new results in all areas of the Materials Science and Engineering. The journal is devoted to the publication of high quality papers on theoretical and practical aspects of Materials Science and Engineering.

The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on Materials Science and Engineering advancements, and establishing new collaborations in these areas. Original research papers, state-of-the-art reviews are invited for publication in all areas of Materials Science and Engineering.  

Topics of Interest include, but are not limited to, the following  

• Art Conservation Science
• Biomaterials, tissue engineering
• Ceramics
• Composites
• Corrosion
• Diffraction studies
• Energy
• Fracture of materials
• Magnetic Materials
• Materials for Electronics and Photonics
• Materials Synthesis & Processing
• Materials Theory, Computation, and Design
• Mechanical properties
• Metals and alloys
• Nanomaterials, Nanoparticulates and nanocomposites
• Polymers
• Self-Assembly
• Solar energy
• Surfaces and Interfaces   

PaperSubmission 
 Authors are invited to submit papers for this journal through Submission System .     Submissions must be original and should not have been published previously or be under   consideration for publication while being evaluated for this Journal.      
Important Dates  

• Submission Deadline   : June 22, 2019
• Authors Notification    : July 22, 2019
• Final Manuscript Due  : July 30, 2019
• Publication date: Determined by the Editor-in-Chief 

Contact Us :      

Here's where you can reach us : msejjournal@airccse.com

Please Visit 

For other details please visit : http://allcfps.com/noncs/submission/index.php

5th International Conference on Signal Processing (SP 2019)

August 24~25, 2019, Vienna, Austria

https://necom2019.org/sp/index.html

IMPORTANT DATES

• Submission Deadline : June 22, 2019

• Authors Notification : July 30, 2019

• Registration & Camera-Ready Paper Due : August 03, 2019 

CONTACT US

Here's where you can reach us : sp.conf@yahoo.com or sp@necom2019.org

5th International Conference on Signal Processing (SP 2019)

https://necom2019.org

HARDWARE EFFICIENT SCALING FREE VECTORING AND ROTATIONAL CORDIC FOR DSP APPLICATIONS

Anita Jain¹ and Kavita Khare²

Department of Electronics and Communication Engineering, MANIT, Bhopal, India

ABSTRACT

The COordinate Rotation DIgital Computer CORDIC algorithm has proved its versatility in computing various transcendental functions by only using the shift and adds operations. This paper presents a new hardware efficient scaling free CORDIC algorithm to operate in vectoring and in rotation mode. The micro rotation of the vector is always in one direction with no scale factor correction. The Range of Convergence RoC is from 0 to 2π. No pre and post processing circuitry is required. 16 bit Scaling free CORDIC Pipelined architecture based on the proposed algorithm is synthesized on FPGA Xilinx VirtexII P device coded in Verilog. Synthesized results show totally scaling free performance with very small dynamic power consumption of .06 mW and maximum delay of 4.123 ns and 9.925 ns in the rotational and vectoring modes respectively. The minimum BEP of the proposed algorithm implementation is 12. Proposed algorithm is faster and efficient in terms of area and accuracy as compared to conventional CORDIC.

KEYWORDS

DSP, Scale Free CORDIC, Systolic array, rotation mode, vectoring mode, RoC, pipeline architecture.

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics02.pdf

http://airccse.org/journal/vlsi/vol4.html

International Journal of VLSI design & Communication Systems( VLSICS )

http://airccse.org/journal/vlsi/vlsics.html

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

Scope & Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include, but are not limited to, the following:

* Design

* VLSI Circuits

* Computer-Aided Design (CAD)

* Low Power and Power Aware Design

* Testing, Reliability, Fault-Tolerance

* Emerging Technologies

* Post-CMOS VLSI

* VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

* Nano Electronics, Molecular, Biological and Quantum Computing

* Intellectual Property Creating and Sharing

* Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through E-mail; vlsicsjournal@airccse.org.  Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates:

·         Submission Deadline    : June 22, 2019

·         Acceptance Notification :  July 22, 2019

·         Final Manuscript Due     :  July 30, 2019

·         Publication Date : Determined by the Editor-in-Chief

For other details please visit: http://airccse.org/journal/vlsi/vlsics.html

SMART MULTICROSSBAR ROUTER DESIGN IN NOC

SMART MULTICROSSBAR ROUTER DESIGN IN NOC 

Bhavana Prakash Shrivastava1 and Kavita Khare2

1Department of Electronics and Communication Engineering, Maulana Azad National Institute of Technology, Bhopal, India

2Department of Electronics and Communication Engineering, Maulana Azad National Institute Of Technology, Bhopal, India

ABSTRACT

This paper gives the innovative idea of designing a router using multicrossbar switch in Network on Chip(NoC) . In Network-on-Chip architectures the input buffer can consume a large portion of the total power. Eliminating all input buffer would result in increased power consumption at high load, while reducing the size of input buffer degrades the performance. In this paper we have proposed a muticrossbar router design using elastic buffer by combining the advantage of both buffered and buffer less network. In the proposed design Power Delay Product is reduced by around 37 .91% as compared to baseline router. 

KEYWORDS

Network on chip, Virtual Channel, Virtual Allocator, Elastic Buffer, Power Delay Product (PDP)

Original Source Link : http://aircconline.com/vlsics/V4N2/4213vlsics07.pdf

http://airccse.org/journal/vlsi/vol4.html

THE DESIGN OF A LOW POWER FLOATING GATE BASED PHASE FREQUENCY DETECTOR AND CHARGE PUMP IMPLEMENTATION

THE DESIGN OF A LOW POWER FLOATING GATE BASED PHASE FREQUENCY DETECTOR AND CHARGE PUMP IMPLEMENTATION

Md Monirul Islam1 and Ankit Shivhare2

1Department of Electronics Engineering, KIIT University, Bhubaneswar, India

2Department of Electronics Engineering, KIIT University, Bhubaneswar, India

ABSTRACT

A simple new architecture of phase frequency detector with low power and low phase noise is presented in this paper. The proposed phase frequency detector is based on floating gate, consist of 4 transistors including one floating gate pMOS and one floating gate nMOS constructed with two GDI (gate diffusion input) cells and maintain main characteristics of conventional phase frequency detector in 180 nm technology. Floating gate based methodology reduced the power of phase frequency detector about 51%. Introduction of floating gate based phased frequency detector also reduces the number of transistor as compared with conventional phase frequency detector.

KEYWORDS

Phase frequency detector, floating gate MOSFET, Voltage controlled oscillator, Gate diffusion cell, Charge pump. 

Original Source Link : http://aircconline.com/vlsics/V4N2/4213vlsics06.pdf

http://airccse.org/journal/vlsi/vol4.html

ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION

ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS FOR MICROWAVE APPLICATIONS

Ramnish Kumar1, Sandeep K Arya1 and Anil Ahlawat2

1Department of ECE, GJUST, Hisar

2Department of CSE, KIET, Ghajiabad

ABSTRACT

An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation. The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have been evaluated to determine the output characteristics, device transconductance and cut-off frequency for 50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been obtained. The results so obtained are in close agreement with experimental data, thereby proving the validity of the model.

KEYWORDS

AlGaN/GaN MODFETs, cut-off frequency, drain - conductance, polarization, trans - conductance. 

Original Source Link : http://aircconline.com/vlsics/V4N2/4213vlsics05.pdf

http://airccse.org/journal/vlsi/vol4.html