DEADLOCK RECOVERY TECHNIQUE IN BUS ENHANCED NOC ARCHITECTURE

DEADLOCK RECOVERY TECHNIQUE IN BUS ENHANCED NOC ARCHITECTURE

Saeid Sharifian Nia1, Abbas Vafaei2, Hamid Shahimohamadi3

1Department of Computer Engineering, University of Isfahan, Isfahan, Iran

2Department of Computer Engineering, University of Isfahan, Isfahan, Iran

3Department of Computer Engineering, Shahid Beheshti University, Tehran, Iran

ABSTRACT

Increase in the speed of processors has led to crucial role of communication in the performance of systems. As a result, routing is taken into consideration as one of the most important subjects of the Network on Chip architecture. Routing algorithms to deadlock avoidance prevent packets route completely based on network traffic condition by means of restricting the route of packets. This action leads to less performance especially in non-uniform traffic patterns. On the other hand True Fully Adoptive Routing algorithm provides routing of packets completely based on traffic condition. However, deadlock detection and recovery mechanisms are needed to handle deadlocks. Use of global bus beside NoC as a parallel supportive environment, provide platform to offer advantages of both features of bus and NoC. This bus is useful for broadcast and multicast operations, sending delay sensitive signals, system management and other services. In this research, we use this bus as an escaping path for deadlock recovery technique. According to simulation results, this bus is suitable platform for deadlock recovery technique. 

KEYWORDS

Network on chip, deadlock recovery, deadlock detection, routing algorithm, bus enhanced NoC. 

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics01.pdf

http://airccse.org/journal/vlsi/vol3.html

EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIFIED BOOTH ALGORITHM AND SPST ADDER USING VERILOG

EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIFIED BOOTH ALGORITHM AND SPST ADDER USING VERILOG

Addanki Purna Ramesh1, Dr.A.V. N. Tilak2 and Dr.A.M.Prasad3

1Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, India

2Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, India

3Department of ECE, UCEK, JNTU, Kakinada, India

ABSTRACT

In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm

MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC

KEYWORDS

Radix -2 modified booth algorithm, Digital signal processing, spurious power suppression Technique, Verilog.

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics10.pdf

http://airccse.org/journal/vlsi/vol3.html

DESIGN AND PERFORMANCE ANALYSIS OF ULTRA LOW POWER 6T SRAM USING ADIABATIC TECHNIQUE

DESIGN AND PERFORMANCE ANALYSIS OF ULTRA LOW POWER 6T SRAM USING ADIABATIC TECHNIQUE

Mr. Sunil Jadav1, Mr. Vikrant2, Dr. Munish Vashisath3

2PG Student, Electrical & Electronics Engineering Dept. YMCAUS&T, Faridabad,Haryana

1,3Faculty, Electrical & Electronics Engineering Dept. YMCAUS&T, Faridabad, Haryana

ABSTRACT: 

Power consumption has become a critical concern in both high performance and portable applications. Methods for power reduction based on the application of adiabatic techniques to CMOS circuits have recently come under renewed investigation. In thermodynamics, an adiabatic energy transfer through a dissipative medium is one in which losses are made arbitrarily small by causing the transfer to occur sufficiently slowly. In this work adiabatic technique is used for reduction of average power

dissipation. Simulation of 6T SRAM cell has been done for 180nm CMOS technology. It shows that average power dissipation is reduced up to 75% using adiabatic technique and also shows the effect on static noise margin.

Keywords

Adiabatic Logic, Average Power dissipation, Static Noise Margin

Original source Link : http://aircconline.com/vlsics/V3N3/3312vlsics09.pdf

http://airccse.org/journal/vlsi/vol3.html

Design of Efficient Adder Circuits Using PROPOSED PARITY PRESERVING GATE (PPPG)

Design of Efficient Adder Circuits Using PROPOSED PARITY PRESERVING GATE (PPPG)

Krishna Murthy M, Gayatri G, Manoj Kumar R

Department of ECE, MVGRCE, Vizianagaram, Andhra Pradesh 

ABSTRACT

Reversible logic is becoming an important research area which aims mainly to reduce power dissipation during computing. In this paper we introduce a new parity preserving reversible gate PPPG (a 5x5 gate). This gate is universal in the sense it can synthesize any arbitrary Boolean function. It is also a parity preserving gate in which the parity of input matches the parity of the output. This parity preserving gate allows any single fault to be detected at the circuit’s primary outputs. By using one PPPG a fault tolerant reversible full adder circuit can be realized. The proposed fault tolerant full adder (PFTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. The PFTFA gate is also used to implement high speed adders which are efficient basic building blocks of logic circuits. It has also been demonstrated that the proposed high speed adders are efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

KEYWORDS

Reversible logic, Garbage output, Reversible gate, Proposed Parity Preserving Gate, Constant inputs and Proposed fault tolerant full adder, Carry Skip Adder, Carry Look Ahead Adder, Ripple carry Adder 

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics08.pdf

http://airccse.org/journal/vlsi/vol3.html

PERFORMANCE EVALUATION OF CDMAROUTER FOR NETWORK - ON - CHIP

PERFORMANCE EVALUATION OF CDMAROUTER FOR NETWORK - ON - CHIP

Anant W. Hinganikar1, Mahendra A. Gaikwad2 and Rajendra M. Patrikar3

1Department of E&T, B.D.College of Engineering, Sevagram (Wardha)-India

2Department of EC, B.D.College of Engineering, Sevagram (Wardha)-India

3Department of EC, VNIT), Nagpur-India

Abstract

This paper presents the performance evaluation of router based on code division multiple access technique (CDMA) for Network-on-Chip (NoC). The design is synthesized using Xilinx Virtex4 XC4VLX200 device. The functional behavior is verified using Modelsim XE III 6.2 C. The delay and throughput values are obtained for variable payload sizes. Throughput-Power and Delay-Power characteristics are also verified for NoC.

Keywords

CDMA, Walsh Code, Router, NoC 

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics07.pdf

http://airccse.org/journal/vlsi/vol3.html

DESIGN AND PERFORMANCE ANALYSIS OF NINE STAGES CMOS BASED RING OSCILLATOR

DESIGN AND PERFORMANCE ANALYSIS OF NINE STAGES CMOS BASED RING OSCILLATOR

Sushil Kumar and Gurjit Kaur

School of Information and Communication Technology Gautam Buddha University, UP, India

ABSTRACT

This paper deals with the design and performance analysis of a ring oscillator using CMOS 45nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS) very large scale integrated circuits (VLSI) is a challenging task for the integrated circuit(IC) designer. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose output oscillates between two voltage levels representing high and low. There are a number of challenges ahead while designing the CMOS Ring Oscillator which are delay, noise and glitches. CMOS is the technology of choice for many applications, CMOS oscillators with low power, phase noise and timing jitter are highly desired. In this paper, we have designed a CMOS ring oscillator with nine stages.Previously, the researchers were unable to reduce the phase noise in ring oscillators substantially with nine stages. We have successfully reduced the phase noise to -6.4kdBc/Hz at 2GHz center frequency of oscillation.

KEYWORDS

Analog and mixed signal (AMS), VLSI circuit, CMOS Ring oscillator (RO), integrated circuit (IC), phase noise, center frequency of oscillation 

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics06.pdf

http://airccse.org/journal/vlsi/vol3.html

A HIGH EFFICIENCY CHARGE PUMP FOR LOW VOLTAGE DEVICES

A HIGH EFFICIENCY CHARGE PUMP FOR LOW VOLTAGE DEVICES

Aamna Anil1 and Ravi Kumar Sharma2

1Department of Electronics and Communication Engineering, Lovely Professional University, Jalandhar, Punjab, India

2Department of Electronics and Communication Engineering, Lovely Professional University, Jalandhar, Punjab, India

ABSTRACT

A charge pump is a kind of DC to DC converter that uses capacitor as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. Charge pumps have been used in the nonvolatile memories, such as EEPROM and Flash memories, for the programming of the floating-gate devices. They can also be used in the low-supply-voltage switched-capacitor systems that require high voltage to drive the analog switched. This paper includes voltage analysis of different charge pumps. On the basis of voltage analysis a new charge pump is proposed. 

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics05.pdf

http://airccse.org/journal/vlsi/vol3.html