Design and test challenges in Nano-scale analog and mixed CMOS technology

Design and test challenges in Nano-scale analog and mixed CMOS technology 

Mouna Karmani, Chiraz Khedhiri and Belgacem Hamdi

Electronics & Microelectronics Laboratory, Monastir, Tunisia

Abstract

The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOS) technology has driven the rapid growth of very large scale integrated (VLSI) circuit for today's high-tech electronics industries from consumer products to telecommunications and computers. As CMOS technologies are scaled down into the nanometer range, analog and mixed integrated circuit (IC) design and testing have become a real challenge to ensure the functionality and quality of the product. The first part of the paper presents the CMOS technology scaling impact on design and reliability for consumer and critical applications. We then propose a discussion on the role and challenges of testing analog and mixed devices in the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects of bridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistive path between VDD supply and the ground. To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp) and a Built in Current Sensor (BICS) to validate the technique and correlate it with post layout simulation results.

Keywords

Nano-CMOS technology, Analog testing, operational amplifier (Op amp), short (bridging) defect, resistive path, IDDQ Testing, BICS, 90nm technology

Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics03.pdf

http://airccse.org/journal/vlsi/vol2.html

A NOVEL APPROACH FOR LOWER POWER DESIGN IN TURBO CODING SYSTEM

A NOVEL APPROACH FOR LOWER POWER DESIGN IN TURBO CODING SYSTEM

Dayadi.Lakshmaiah1,  Dr.M.V.Subramanyam2 and Dr.K.Sathaya Prasad3

1Asso.professor of ECE Department, Sree Dattha Engineering and Science, India.

2Principal and Professorof ECE Department, Santhi Ram Engineering College, India.

3Professor of ECE Department and Rector, JNTU Kakinada, Kakinada, India. 

Abstract

Low Power is an extremely important issue for future mobile communication systems; The focus of this paper is to implementat turbo codes for low power solutions. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleave in the presence of additive white Gaussian noise is studied with the floating point model. In order to obtain the effect of quantization and word length variation, a fixed point model of the application is also developed.. The application performance measure, namely bit-error rate (BER) is used as a design constraint while optimizing for power and area coverage. Low power Optimization is Performed on Implementation levels by the use of Voltage scaling. With those Techniques we can reduced the power 98.5%and Area(LUT) is 57% and speed grade is Increased .This type of Power maneger is proposed and implemented based on the timing details of the turbo decoder in the VHDL model. 

Keywords

low power consumption, Turbo Encoder, Turbo Decoder, Power Ooptimization, AreaOptimization. 

Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics02.pdf

http://airccse.org/journal/vlsi/vol2.html

A BIST GENERATOR CAD TOOL FOR NUMERIC INTEGRATED CIRCUITS

A BIST GENERATOR CAD TOOL FOR NUMERIC INTEGRATED CIRCUITS
Chiraz Khedhiri1, Mouna Karmani1 and Belgacem Hamdi1,2

1Electronic & Microelectronics’LAB, Monastir, Tunisia

2ISSAT, Sousse, Tunisia

ABSTRACT

This paper describes a training and research tool for learning basic issues related to BIST (Built-In SelfTest) generator. The main didactic aim of the tool is presenting complicated concepts in a comprehensive graphical and analytical way. The paper describes a computer-aided design (CAD) that is used to generate automatically the BIST to any digital circuit. This software technique attempts to reduce the amount of extra hardware and cost of the circuit. In order to make our software being easily available, we used the Java platform, which is supported by most operating systems. The multi-platform JAVA runtime environment allows for easy access and usage of  the tool.

KEYWORDS

BIST generator, test, Computer-Aided Design, Tool, Linear Feedback Shift Register, Single/Multiple Input Signature Register, fault.

Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics01.pdf

http://airccse.org/journal/vlsi/vol2.html

AREA EFFICIENT 3.3GHZ PHASE LOCKED LOOP WITH FOUR MULTIPLE OUTPUT USING 45NM VLSI TECHNOLOGY

AREA EFFICIENT 3.3GHZ PHASE LOCKED LOOP WITH FOUR MULTIPLE OUTPUT USING 45NM VLSI TECHNOLOGY

Ms. Ujwala A. Belorkar 1 and Dr. S.A.Ladhake2

1Department of electronics & telecommunication ,Hanuman Vyayam Prasarak Mandal’s, College of Engineering & Technology, Amravati. Maharashtra.

2Sipana’s College of Engineering & Technology, Amravati, Maharashtra. 

Abstract 

This paper present area efficient layout designs for 3.3GigaHertz (GHz) Phase Locked loop (PLL) with four multiple output. Effort has been taken to design Low Power Phase locked loop with multiple output, using VLSI technology. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD and practical experience in layout design. The proposed PLL is designed using 45 nm CMOS/VLSI technology with microwind 3.1. This software allows designing and simulating an integrated circuit at physical description level. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate length required for 45 nm technology is 25nm. Low Power (0.211miliwatt) phase locked loop with four multiple outputs as PLL8x, PLL4x, PLL2x, & PLL1x of 3.3 GHz, 1.65 GHz, 0.825 GHz, and 0.412 GHz respectively is obtained using 45 nm VLSI technology. 

KeyWord:

phase-locked loop (PLL), high performance voltage-controlled oscillator (VCO), 45nm technology, multiple outputs, low power

Original Source Link : http://aircconline.com/vlsics/V2N1/2111vlsics10.pdf

http://airccse.org/journal/vlsi/vol2.html

Design and Analysis of Second and Third Order PLL at 450MHz

B. K. Mishra1, Sandhya Save2, Swapna Patil1

1 Department of Electronics and Telecommunication Engineering,TCET, Mumbai University, India 

2 Department of Electronics Engineering, TCET,Mumbai University, India

ABSTRACT

Designing of an analog circuit satisfying the design constraints for desired application is a challenging job. Phase Lock Loop (PLL) is an important analog circuit used in various communication applications such as frequency synthesizer, radio, computer, clock generation, clock recovery, global positioning system, etc. Since all these applications are operating at different frequency, satisfying design constraints for PLL with respect to type of PLL operating frequency, Bandwidth, Settling time and other parameters is an critical and time consuming issue. In this paper, selection and design for Second order and third order PLL suggested using MATLAB, Simulink as a simulation tool. The simulated results for the design PLL at 450 MHz indicates good accuracy when the behavior model is compared with the mathematical model. Finally the performance of PLL is tested and calculated for parameters like lock time, lock range, Bandwidth. 

KEYWORDS

PLL, Charge Pump PLL, Baseband PLL, VCO, Simulink, CAD, EDA tool.

Original Source Link : http://aircconline.com/vlsics/V2N1/2111vlsics09.pdf

http://airccse.org/journal/vlsi/vol2.html

DESIGN APPROACH FOR FAULT TOLERANCE IN FPGA ARCHITECTURE

DESIGN APPROACH FOR FAULT TOLERANCE IN FPGA ARCHITECTURE

Ms. Shweta S. Meshram 1 and Ms. Ujwala A. Belorkar 2 

1Department of electronics & telecommunication, Government College of Engineering & Technology, Amravati, India

2 Department of electronics & telecommunication, Hanuman Vyayam Prasarak Mandal’s College of Engineering & Technology, Amravati, India

Abstract 

Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain hardware redundancy to allow for continued operation in the presence of operational faults, the need to recover faulty hardware and return it to full functionality quickly and efficiently is great. In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults in the field. Reliability and process variability are serious issues for FPGAs in the future. With advancement in process technology, the feature size is decreasing which leads to higher defect densities, more sophisticated techniques at increased costs are required to avoid defects. If nano-technology fabrication are applied the yield may go down to zero as avoiding defect during fabrication will not be a feasible option Hence, feature architecture have to be defect tolerant. In regular structure like FPGA, redundancy is commonly used for fault tolerance. In this work we present a solution in which configuration bit-stream of FPGA is modified by a hardware controller that is present on the chip itself. The technique uses redundant device for replacing faulty device and increases the yield. 

Key Word

Fault tolerance, FPGA, hardware controller, redundancy. 

Original Source Link : http://aircconline.com/vlsics/V2N1/2111vlsics08.pdf

http://airccse.org/journal/vlsi/vol2.html

Design of a high frequency low voltage CMOS operational amplifier

Design of a high frequency low voltage CMOS operational amplifier

Priyanka Kakoty

Department of Electronics and Communication Engineering, Tezpur University, India 

ABSTRACT

A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit. 

KEYWORDS

CMOS Analog Circuit, Operational amplifier, Current Buffer Compensation, High Frequency, Low Voltage 

Original Source Link : http://aircconline.com/vlsics/V2N1/2111vlsics07.pdf

http://airccse.org/journal/vlsi/vol2.html

IMPACT OF STRAIN AND CHANNEL THICKNESS ON PERFORMANCE OF BIAXIAL STRAINED SILICON MOSFETs

IMPACT OF STRAIN AND CHANNEL THICKNESS ON PERFORMANCE OF BIAXIAL STRAINED SILICON MOSFETs 

Neha Sharan, Ashwani K.Rana

Department of Electronics and Communication, National Institute of Technology, India

ABSTRACT

In this paper the impact of strain and channel thickness on the performance of biaxial strained silicon MOSFET with 40 nm channel length has been analyzed by simulation in TCAD Sentaurus Simulator. With the increase in the mole fraction of germanium at the interface of the channel region, the strain in the silicon channel increases and with it the mobility of the carriers increases and thus the drain current increases. The mole fraction in this paper is varied from 0 to 0.3. Other than mobility, the increase in strain also shows improvement in other performance parameters. The impact of variation in channel thickness on the functionality parameters of the MOSFET has also been analyzed. The channel thickness cannot be increased more than the critical thickness and therefore, in this paper the thickness is varied from 2nm to 20 nm. It is observed that beyond 10nm the performance improvement gets saturated and therefore the critical thickness for the channel of this structure is 10nm..

KEYWORDS

Biaxial Strained, Channel Thickness, Drain current, Mobility & Mole Fraction. 

Original ource Link : http://aircconline.com/vlsics/V2N1/2111vlsics06.pdf

http://airccse.org/journal/vlsi/vol2.html

OPTIMIZATION TECHNIQUES FOR SOURCE FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR HIGH SPEED WIRELESS COMMUNICATION

OPTIMIZATION TECHNIQUES FOR SOURCE FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR HIGH SPEED WIRELESS COMMUNICATION

Manoj Kumar1 and Gagnesh Kumar2

Department of Electronics & Comm, Vidya College of Engg., Meerut (U.P)

Department of Electronics & Comm, NIT Hamirpur, Hamirpur (H.P)

ABSTRACT

Since the current demand for high-resolution and fast analog to digital converters (ADC) is driving the need for track and hold amplifiers (T&H) operating at RF frequencies. A very fast and linear T&H circuit is the key element in any modern wideband data acquisition system. Applications like a cable TV or a broad variety of different radio standards require high processing speeds with high resolution. The track-and-hold (T&H) circuit is a fundamental block for analog-to digital (A/D) converters. Its use allows most dynamic errors of A/D converters to be reduced, especially those showing up when using high frequency input signals. Having a wideband and precise acquisition system is a prerequisite for today’s trend towards multi-standard flexible radios, with as much signal processing as possible in digital domain. This work investigates effect of various design schemes and circuit topology for track and-hold circuit to achieve acceptable linearly, high slew rate, low power consumption and low noise

KEYWORDS

Track and Hold Circuit, Low Power Consumption, Slew Rate, Peak Power, Sampling Switch, Flash 

 Analog to Digital Converter 

Original Source Link : http://aircconline.com/vlsics/V2N1/2111vlsics05.pdf

http://airccse.org/journal/vlsi/vol2.html

DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOP

DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOP

R.Jayagowri1 and K.S.Gurumurthy2 

1Research Scholar, Department of Electronics and Communication Engineering,Jawaharlal Nehru Technological University, Hyderabad, India

2Professor, Department of Electronics and Communication Engineering, University,Visveswaraya College of Engineering, Bangalore, India

ABSTRACT

The power consumption of IC during test mode is higher than its normal mode. This brings the power as one of the major design constraints for today’s low power design technologies. In normal scan based test circuits most of the power consumed due to the switching activity of scanflops during shift and capture cycles. In this paper a novel scanflop is presented which reduces the switching activity of the scanflop for clock and it reduces the power consumption of the circuit and it also reduces area and test time too. The proposed Dual Mode One Latch Double Edge Triggered (DMOL-DET) scanflop which shift the two bits of test vector in a clock cycle, during its test mode and captures the single data in a clock cycle during its data mode. The design and functionality of the proposed scanflop is discussed and compared with the different flipflops which shows that the proposed scan flop reduces the test time and clock switching activity by 50%, area by 30% and static power by 25%. 

Keywords

Scanflop, Double edge triggered flipflop, test time, low power, Latch, Testing, Scan chain. 

Original Source Link : http://aircconline.com/vlsics/V2N1/2111vlsics04.pdf

http://airccse.org/journal/vlsi/vol2.html

Physical Scaling Limits of FinFET Structure: A Simulation Study

Physical Scaling Limits of FinFET Structure: A Simulation Study

Gaurav Saini1, Ashwani K Rana2

 National Institute of Technology Hamirpur, India

Abstract

In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length (L) and fin-thickness (Tfin) ratio plays a key role while deciding the performance of the device. Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/Tfin) ratio goes below 1.5. So, there will be a trade-off in between SCEs and on- current of the device since on-off current ratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found that both fin-thickness (Tfin) and fin-height (Hfin) can control the SCEs. However, Tfin is found to be more dominant parameter than Hfin while deciding the SCEs. DIBL and SS increase as (Leff/Tfin) ratio decreases. The (Leff/Tfin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However, as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. The relative ratio of Hfin and Tfin should be maximum at a given Tfin and Leff to get maximum on-current per unit width. However, increasing Hfin degrades the fin stability and degrades SCEs.

Keywords

Double Gate, Triple Gate, Underlap, Overlap, FinFET, High performance (HP), ITRS 

Original Source Link : http://aircconline.com/vlsics/V2N1/2111vlsics03.pdf

http://airccse.org/journal/vlsi/vol2.html

HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFECT TRANSISTOR

HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFECT TRANSISTOR

Ashkan Khatir1, Shaghayegh Abdolahzadegan2, Iman Mahmoudi

Islamic Azad University,Science and Research Branch, Tehran, Iran

Abstract

High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.

KEYWORDS

Mulitple Valued Logic; Carbon NanoTube; Carbon Nanotube Field Effect Transistor; Full Adder; High Speed 

Original Source Link : http://aircconline.com/vlsics/V2N1/2111vlsics01.pdf

http://airccse.org/journal/vlsi/vol2.html

Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory

Subashri T1, Arunachalam R2, Gokul Vinoth Kumar B3, Vaidehi V4

Department of Electronics, MIT Campus, Anna University, Chennai-44

Abstract.

A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.

Keywords

AES pipelining, Key pipelining, Search Based Memory, VLSI.

Original Source Link : http://aircconline.com/vlsics/V1N4/1210vlsics05.pdf

http://airccse.org/journal/vlsi/vol1.html

Design and Analysis of Multi Vt  and Variable Vt based Pipelined Adder for Low Power applications 

Shanthala S1, Cyril Prasanna Raj P2, Dr. S.Y.Kulkarni3

1 Research Scholar in EC Research Centre, NMAMIT, Nitte 

ABSTRACT

Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications. 

.

KEYWORDS

DSP, MAC, CMOS, Pipeline, Static and Dynamic

Original Source Link : http://aircconline.com/vlsics/V1N4/1210vlsics04.pdf

http://airccse.org/journal/vlsi/vol1.html

SINGLE ELECTRON TRANSISTOR: APPLICATIONS & PROBLEMS

SINGLE ELECTRON TRANSISTOR: APPLICATIONS & PROBLEMS

Om Kumar1 and Manjit Kaur2

1, 2 VLSI-ES Department, Centre for Development of Advanced Computing, Mohali, India

ABSTRACT

The goal of this paper is to review in brief the basic physics of nanoelectronic device single-electron transistor [SET] as well as prospective applications and problems in their applications. SET functioning based on the controllable transfer of single electrons between small conducting "islands". The device properties dominated by the quantum mechanical properties of matter and provide new characteristics coulomb oscillation, coulomb blockade that is helpful in a number of applications. SET is able to shear domain with silicon transistor in near future and enhance the device density. Recent research in SET gives new ideas which are going to revolutionize the random access memory and digital data storage technologies.

Keywords

Nanoelectronics; Single-electron transistor; Coulomb blockade, Coulomb oscillation, Quantum dot

Originl Source Link : http://aircconline.com/vlsics/V1N4/1210vlsics03.pdf

http://airccse.org/journal/vlsi/vol1.html

SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SUBMICRON TECHNOLOGY

SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SUBMICRON TECHNOLOGY

T. Suguna and M. Janaki Rani

Department of Electronics and Communication Engineering,

Dr.M.G. R Educational and Research Institute, Chennai, India

ABSTRACT

CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.

KEYWORDS

leakage power, low power, voltage scaling, power gating, transistor stacking, adiabatic logic. 

Original Source Link :http://aircconline.com/vlsics/V9N1/9118vlsi01.pdf

http://airccse.org/journal/vlsi/current.html

A CONTEMPORARY SURVEY ON ENERGY HARVESTING TECHNIQUES FOR NEXT GENERATION IMPLANTABLE BIO-MEDICAL DEVICES

A CONTEMPORARY SURVEY ON ENERGY HARVESTING TECHNIQUES FOR NEXT GENERATION IMPLANTABLE BIO-MEDICAL DEVICES

Mrs.J.Jeneetha Jebanazer1 and Dr.M.Janakirani2

1Department of ECE, Panimalar Engineering College, Chennai

2Dr.MGR Educational and Research Institute University, Chennai

ABSTRACT

Providing a constant and perpetual energy source is a key design challenge for implantable medical devices. Harvesting energy from the human body and the surrounding is one of the possible solutions. Delivering energy from outside the body through different wireless media is another feasible solution. In this paper, we review different state-of-the-art methods that process “in-body” energy harvesting as wellas “out-of-body" wireless power delivery. Details of the energy sources, transmission media, energy harvesting, coupling techniques and the required energy transducers will also be discussed. The merits and disadvantages of each approach will be presented. Different types of mechanisms have very different characteristics on their output voltage, amount of harvested power and power transfer efficiency. Therefore different types of power conditioning circuits are required. Issues of designing the building blocks for the power conditioning circuits for different energy harvesting or coupling mechanisms will be compared.

KEYWORDS

Energy Harvesting, Impalntablr Bio-Medical Devices , Pacemaker, Power Delivery, Sensors

Original Source Link : http://aircconline.com/vlsics/V9N2/9218vlsi02.pdf

http://airccse.org/journal/vlsi/current.html

HARDWARE SECURITY IN CASE OF SCAN-BASED ATTACK ON CRYPTO-HARDWARE

HARDWARE SECURITY IN CASE OF SCAN-BASED ATTACK ON CRYPTO-HARDWARE

Jayesh Popat1 and Usha Mehta2

1&2 EC Department, Nirma University, Gujarat, India

ABSTRACT

The latest innovation technology in computing devices has given a rise of compact, speedy and economical products which also embeds cryptography hardware on-chip. This device generally holds secret key and confidential information, more attention has been given to attacks on hardware which guards such secure information. The attacker may leak secret information from symmetric crypto-hardware (AES, DES etc.) using side-channel analysis, fault injection or exploiting existing test infrastructure. This paper examines various DFT based attack implementation method applied to cryptographic hardware. The paper contains an extensive analysis of attacks based on various parameters. The countermeasures are classified and analyzed in details.

KEYWORDS

Hardware Security, Cryptography, Side-channel analysis, fault injection, scan-based attack, testability, security.

Original Source Link : http://aircconline.com/vlsics/V9N2/9218vlsi01.pdf

http://airccse.org/journal/vlsi/current.html