SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBY

SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBY

Chien-Cheng Yu^1* and Ming-Chuen Shiau²

¹Dept. of Electronic Engineering,

Hsiuping University of Science and Technology, Taichung, Taiwan

²Dept. of Electrical Engineering,

Hsiuping University of Science and Technology, Taichung, Taiwan

ABSTRACT

In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid unnecessary power consumption. Finally, with the standby start-up circuit design, the cell can switch to the standby mode quickly, thereby reduce leakage current in standby.

KEYWORDS

Static random access memory, Read/write assist circuitry, Voltage control circuit, Standby start-up circuit 

Original Source URL :

http://aircconline.com/vlsics/V7N4/7416vlsi01.pdf

For More Details :

http://airccse.org/journal/vlsi/vlsics.html