REDUCED COMPLEXITY QUASI-CYCLIC LDPC ENCODER FOR IEEE 802.11N

REDUCED COMPLEXITY QUASI-CYCLIC LDPC ENCODER FOR IEEE 802.11N

Monica Mankar¹, Gajendra Asutkar², Pravin Dakhole³

¹Research Scholar Department of Electronics Engineering,

Yeshwantrao Chavan college of Engineering., Nagpur, India.

²Professor, Department of Electronics and communication Engineering,

Priyadarshani Institute of Engineering and technology Nagpur, India

³Professor,Department of Electronics Engineering ,

Yeshwantrao Chavan college of Engineering., Nagpur, India 

ABSTRACT

In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder hardware based on Richardson and Urbanke lower- triangular algorithm for IEEE 802.11n wireless LAN Standard for 648 block length and 1/2 code rate. The LDPC encoder hardware implementation works at 301.433MHz and it can process 12.12 Gbps throughput. We apply the concept of multiplication by constant matrices in GF(2) due to which hardware required is also optimized. Proposed architecture of QC-LDPC encoder will be compatible for high-speed applications. This hardwired architecture is less complex as it avoids conventionally used block memories and cyclic-shifters.

KEYWORDS

Quasi-cyclic -low-density-parity-check (QC-LDPC), WLAN (IEEE802.11n), Richardson and Urbanke lower- triangular algorithm, encoder 

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