Heuristic approach to optimize the number of test cases for simple circuits

Heuristic approach to optimize the number of test cases for simple circuits

SM. Thamarai1, K.Kuppusamy2 and T. Meyyappan
Department of Computer Science and Engineering, Alagappa University, Tamilnadu, South India.

ABSTRACT

In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circuit. The main idea behind the present research work is to identify the maximum number of indistinguishable faults present in the given circuit and minimize the number of test cases based on the number of faults that has been detected. Heuristic approach is used for test minimization part, which identifies the essential tests from overall test cases. From the results it is observed that, test minimization varies from 50% to 99% with the lowest one corresponding to a circuit with four gates .Test minimization is low in case of circuits with lesser input leads in gates compared to greater input leads in gates for the boolean expression with same number of symbols. Achievement of 99% reduction is due to the fact that the large number of tests find the same faults. The new approach is implemented for simple circuits. The results show potential for both smaller test sets and lower cpu times.

KEYWORDS

Adaptive Scheduled Fault Detection, Combinational Circuits, Fault Library, Heuristic Approach , Test Minimization.

Original Source Link : http://aircconline.com/vlsics/V1N3/0910vlsics02.pdf
http://airccse.org/journal/vlsi/vol1.html