Low Power Reversible Parallel Binary Adder/Subtractor

Low Power Reversible Parallel Binary Adder/Subtractor
Rangaraju H G1, Venugopal U2, Muralidhara K N3, Raja K B 2
1Department of Telecommunication Engineering, Bangalore Institute of Technology, Bangalore, India
2Department of Electronics and Communication Engineering, University Visvesvaraya College of Engineering, Bangalore, India
3Department of Electronics and Communication Engineering, P E S College of Engineering, Mandya, Karnataka, India

Abstract

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.

Keywords

Reversible Logic, Garbage Input/output, Quantum Cost, Low Power, Reversible Parallel Binary Adder/Subtractor. 

Original Source Link : http://aircconline.com/vlsics/V1N3/0910vlsics03.pdf
http://airccse.org/journal/vlsi/vol1.html