A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register (MISR)

A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register (MISR)
Afaq Ahmad
Department of Electrical and Computer Engineering College of Engineering, Sultan Qaboos University , Sultanate of Oman 


ABSTRACT

This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (Multi-Input Shift Register), used in an LFSR based digital circuit testing technique. The investigation is carried-out through an extensive simulation study of the effectiveness of the LFSR based digital circuit testing technique. The results of the study show that when the identical characteristic polynomials of order n are used in both pseudo-random test-pattern generator, as well as in Multi-Input Shift Register (MISR) signature analyzer (parallel type) then the probability of aliasing errors remains unchanged due to the changes in the initial loadings of the pseudo-random test-pattern generator.

KEYWORDS

LFSR, MISR, BIST, Characteristic Polynomial, Primitive 

Original Source Link : http://aircconline.com/vlsics/V1N4/1210vlsics01.pdf
http://airccse.org/journal/vlsi/vol1.html

DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PROGRAMMABILITY USING FLOATING-GATE TRANSISTORS

DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PROGRAMMABILITY USING FLOATING-GATE TRANSISTORS

Garima Kapur1, C.M Markan2 and V. Prem Pyara3
1&2 Department of Physics and Computer Science, Dayalbagh Educational Institute, INDIA 
3Department of Electrical Engineering, Dayalbagh Educational Institute, INDIA 

ABSTRACT

This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.

KEYWORDS

Square wave generator, floating gate FET, field programmability

Original Source Link : http://aircconline.com/vlsics/V1N3/0910vlsics05.pdf
http://airccse.org/journal/vlsi/vol1.html

Low Power Reversible Parallel Binary Adder/Subtractor

Low Power Reversible Parallel Binary Adder/Subtractor
Rangaraju H G1, Venugopal U2, Muralidhara K N3, Raja K B 2
1Department of Telecommunication Engineering, Bangalore Institute of Technology, Bangalore, India
2Department of Electronics and Communication Engineering, University Visvesvaraya College of Engineering, Bangalore, India
3Department of Electronics and Communication Engineering, P E S College of Engineering, Mandya, Karnataka, India

Abstract

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.

Keywords

Reversible Logic, Garbage Input/output, Quantum Cost, Low Power, Reversible Parallel Binary Adder/Subtractor. 

Original Source Link : http://aircconline.com/vlsics/V1N3/0910vlsics03.pdf
http://airccse.org/journal/vlsi/vol1.html

Heuristic approach to optimize the number of test cases for simple circuits

Heuristic approach to optimize the number of test cases for simple circuits

SM. Thamarai1, K.Kuppusamy2 and T. Meyyappan
Department of Computer Science and Engineering, Alagappa University, Tamilnadu, South India.

ABSTRACT

In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circuit. The main idea behind the present research work is to identify the maximum number of indistinguishable faults present in the given circuit and minimize the number of test cases based on the number of faults that has been detected. Heuristic approach is used for test minimization part, which identifies the essential tests from overall test cases. From the results it is observed that, test minimization varies from 50% to 99% with the lowest one corresponding to a circuit with four gates .Test minimization is low in case of circuits with lesser input leads in gates compared to greater input leads in gates for the boolean expression with same number of symbols. Achievement of 99% reduction is due to the fact that the large number of tests find the same faults. The new approach is implemented for simple circuits. The results show potential for both smaller test sets and lower cpu times.

KEYWORDS

Adaptive Scheduled Fault Detection, Combinational Circuits, Fault Library, Heuristic Approach , Test Minimization.

Original Source Link : http://aircconline.com/vlsics/V1N3/0910vlsics02.pdf
http://airccse.org/journal/vlsi/vol1.html

A High-Swing OTA with wide Linearity for design of self-tunable linear resistor

A High-Swing OTA with wide Linearity for design of self-tunable linear resistor
Nikhil Raj, R.K.Sharma
Department of Electronics and Communication Engineering, National Institute of Technology, India

ABSTRACT

Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.

KEYWORDS

Bulk-input, Wilson mirror, Linear range, MOS resistor

Original Source Link : http://aircconline.com/vlsics/V1N3/0910vlsics01.pdf
http://airccse.org/journal/vlsi/vol1.html

MINIMIZATION OF HANDOFF LATENCY BY CO-ORDINATE EVALUATION METHOD USING GPS BASED MAP

MINIMIZATION OF HANDOFF LATENCY BY CO-ORDINATE EVALUATION METHOD USING GPS BASED MAP
Debabrata Sarddar1, Joydeep Banerjee1, Souvik Kumar Saha1, Tapas Jana2,Utpal Biswas3 and M.K. Naskar1
1 Department of Electronics and Telecommunication Engg, Jadavpur University, Kolkata, India
2. Department of Electronics and Communication Engg, Netaji Subhash Engg College, Techno City, Garia, Kolkata, India
3. Department of Computer Science and Engg, University of Kalyani, Nadia, West Bengal

ABSTRACT

Handoff has become an essential criterion in mobile communication system, specially in urban areas, owing to the limited coverage area of Access Points (AP). Handover of calls between two BS is encountered frequently and it is essentially required to minimize the delay of the process. Many solutions attempting to improve this process have been proposed but only a few use geo-location systems in the management of the handover. Here we propose to minimize the handoff latency by minimizing the number of APs scanned by the mobile node (MN) during each handoff procedure. We consider the whole topographical area as a two dimensional plane. By GPS, we can note down the co-ordinates of the MN at any instant. The average rate of change of its latitudinal distance and longitudinal distance with a specific time period is evaluated at the end of the given time period. With the knowledge of the given parameter, it is possible to determine the latitude and longitude of the MN after a particular instant of time. Hence the direction of motion of the MN can be determined which in turns gives the AP towards which the MN is heading towards. This reduces the number of APs to be scanned. Thus, on an overall basis, the handoff latency can be reduced by almost half to on third of its value.

KEYWORDS

IEEE 802.11,GPS (Global Positioning System), trajectory of MN, Neighbor APs, co-ordinate evaluation. 

Original Source Link : http://aircconline.com/vlsics/V1N2/0610vlsics4.pdf
http://airccse.org/journal/vlsi/vol1.html

TWO DIMENSIONAL MODELING OF NONUNIFORMLY DOPED MESFET UNDER ILLUMINATION

TWO DIMENSIONAL MODELING OF NONUNIFORMLY DOPED MESFET UNDER ILLUMINATION
Dr B.K.Mishra1, Lochan Jolly2 and Kalawati Patil3
1 Principal,Thakur College of Engg and Technology, Mumbai, India

2,3 Department of Electronics and Telecommunication, Thakur College of Engg and Technology, Mumbai, India

ABSTRACT

A two dimensional numerical model of an optically gated GaAs MESFET with non uniform channel doping has been developed. This is done to characterize the device as a photo detector. First photo induced voltage (Vop) at the Schottky gate is calculated for estimating the channel profile. Then Poisson’s equation for the device is solved numerically under dark and illumination condition. The paper aims at developing the MESFET 2-D model under illumination using Monte Carlo Finite Difference method. The results discuss about the optical potential developed in the device, variation of channel potential under different biasing and illumination and also about electric fields along X and Y directions. The Cgs under different illumination is also calculated. It has been observed from the results that the characteristics of the device are strongly influenced by the incident optical illumination.

KEYWORDS

Optoelectronics, Schottky Junction, Photodetectors, Photovoltage

Original Source Link : http://aircconline.com/vlsics/V1N2/0610vlsics3.pdf

http://airccse.org/journal/vlsi/vol1.html

EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION SYSTEMS

EFFICIENT HARDWARE CO-SIMULATION OF DOWN CONVERTOR FOR WIRELESS COMMUNICATION SYSTEMS

Rajesh Mehra1 and Swapna Devi2

1,2Department of Electronics & Communication Engineering, NITTTR, India

ABSTRACT

In this paper an optimized hardware co-simulation approach is presented to design & implement GSM based digital down convertor for Software Defined Radios. The proposed DDC is implemented using optimal equiripple technique to reduce the resource requirement. A computationally efficient polyphase decomposition structure is used to improve the hardware complexity of the overall design. The proposed model is implemented by using embedded multipliers, LUTs and BRAMs of target device to enhance the system performance in terms of speed and area. The DDC model is designed and simulated with Simulink and Xilinx System Generator, synthesized with Xilinx Synthesis Tool (XST) and implemented on Virtex-II Pro based xc2vp30-7ff896 FPGA device. The results show that proposed design can operate at maximum frequency of 160 MHz by consuming power of 0.34004W 25 °C junction temperature. The proposed design is consuming very less resources available on target device to provide cost effective solution for SDR based wireless applications.

KEYWORDS

ASIC, BRAM, FPGA, GSM, LUT & SDR 

Original Source Link : http://aircconline.com/vlsics/V1N2/0610vlsics2.pdf

http://airccse.org/journal/vlsi/vol1.html

DESIGN OF LOW POWER PHASE LOCKED LOOP (PLL) USING 45NM VLSI TECHNOLOGY

DESIGN OF LOW POWER PHASE LOCKED LOOP (PLL) USING 45NM VLSI TECHNOLOGY

Ms. Ujwala A. Belorkar1 and Dr. S.A.Ladhake2

1Department of electronics & telecommunication ,Hanuman Vyayam Prasarak Mandal’s College of Engineering & Technology, India.

2Sipana’s College of Engineering & Technology, India 

ABSTRACT

Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core of a microprocessor, which includes the largest power density on the microprocessor. In an effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. Lowering the supply voltage, however, also reduces the performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available in some application domains, is to replicate the circuit block whose supply voltage is being reduced in order to maintain the same throughput .This paper introduces a design aspects for low power phase locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. The main novelty related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD, practical experience in layout design 

KEYWORDS

Phase locked loop (PLL), voltage-controlled oscillator (VCO), 45nm technology, VLSI technology, low power

Original Source Link : http://aircconline.com/vlsics/V1N2/0610vlsics1.pdf

http://airccse.org/journal/vlsi/vol1.html

Design of A Low Power Low Voltage CMOS Opamp

Design of A Low Power Low Voltage CMOS Opamp
Ratul Kr. Baruah
Department of Electronics and Communication Engineering, Tezpur University, India


ABSTRACT

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1uA input bias current at 0.8 um technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 um

technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2 ) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.

KEYWORDS

Opamp, Adaptive biasing, Low power, Low voltage, Current Substractor.

Original Source URL :

http://aircconline.com/vlsics/V1N1/0310vlsics1.pdf 

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http://airccse.org/journal/vlsi/vol1.html 

DESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCO

DESIGN OF DIGITAL PLL USING OPTIMIZED PHASE NOISE VCO

Purnima¹, Radha B.L² and Kumaraswamy K.V³

¹PG student, Department of ECE, Bangalore Institute of Technology, Bengaluru, India

²Associate professor, Department of ECE,

Bangalore Institute of Technology, Bengaluru, India

³Technical Manager, Trident Techlabs Private limited, Bengaluru, India

ABSTRACT

This paper emphasizes the CMOS implementation of PLL in 130nm technology using Mentor Graphics tool Pyxis. Most of the PLL uses VCO which depends upon variation of supply voltage for high tuning range. Whenever supply voltage changes, the stability will be effected by producing large variations in the frequency output. Since this paper gives the design of current starved or integrator VCO with Schmitt trigger circuit for PLL architecture where instead of varying supply varying the control voltage. In this paper transient analysis, phase noise analysis and jitter analysis of PLL is introduced. This low jittery PLL is further applicable in frequency synthesis, clock recovery that is mainly applicable for wireless communication systems. The PLL gets locked by producing output frequency 1.318GHz with -130dBc/Hz at offset of 10MHz and with cycle to cycle jitter of 5.98ps along with period jitter RMS of 4.92ns. The phase margin is also improved which is 66.280.

KEYWORDS

PD (Phase Detector), LPF (Low Pass Filter), VCO (Voltage Controlled Oscillator), PLL (Phase Locked Loop), PN (Phase noise analysis), SNR (Signal to Noise ratio), ENOR (Equivalent number of bits), BER (Bit Error Rate)

Original Source URL :

http://aircconline.com/vlsics/V7N4/7416vlsi02.pdf

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SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBY

SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBY

Chien-Cheng Yu^1* and Ming-Chuen Shiau²

¹Dept. of Electronic Engineering,

Hsiuping University of Science and Technology, Taichung, Taiwan

²Dept. of Electrical Engineering,

Hsiuping University of Science and Technology, Taichung, Taiwan

ABSTRACT

In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid unnecessary power consumption. Finally, with the standby start-up circuit design, the cell can switch to the standby mode quickly, thereby reduce leakage current in standby.

KEYWORDS

Static random access memory, Read/write assist circuitry, Voltage control circuit, Standby start-up circuit 

Original Source URL :

http://aircconline.com/vlsics/V7N4/7416vlsi01.pdf

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REDUCED COMPLEXITY QUASI-CYCLIC LDPC ENCODER FOR IEEE 802.11N

REDUCED COMPLEXITY QUASI-CYCLIC LDPC ENCODER FOR IEEE 802.11N

Monica Mankar¹, Gajendra Asutkar², Pravin Dakhole³

¹Research Scholar Department of Electronics Engineering,

Yeshwantrao Chavan college of Engineering., Nagpur, India.

²Professor, Department of Electronics and communication Engineering,

Priyadarshani Institute of Engineering and technology Nagpur, India

³Professor,Department of Electronics Engineering ,

Yeshwantrao Chavan college of Engineering., Nagpur, India 

ABSTRACT

In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder hardware based on Richardson and Urbanke lower- triangular algorithm for IEEE 802.11n wireless LAN Standard for 648 block length and 1/2 code rate. The LDPC encoder hardware implementation works at 301.433MHz and it can process 12.12 Gbps throughput. We apply the concept of multiplication by constant matrices in GF(2) due to which hardware required is also optimized. Proposed architecture of QC-LDPC encoder will be compatible for high-speed applications. This hardwired architecture is less complex as it avoids conventionally used block memories and cyclic-shifters.

KEYWORDS

Quasi-cyclic -low-density-parity-check (QC-LDPC), WLAN (IEEE802.11n), Richardson and Urbanke lower- triangular algorithm, encoder 

Original Source URL :

http://aircconline.com/vlsics/V7N6/7616vlsi04.pdf

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500nW A LOW POWER SWITCHED CAPACITOR BASED ACTIVE LOW PASS FILTER FOR BIOMEDICAL APPLICATIONS

500nW A LOW POWER SWITCHED CAPACITOR BASED ACTIVE LOW PASS FILTER FOR BIOMEDICAL APPLICATIONS

U. Gnaneshwara chary, L.Babitha and Vandana.Ch

Department of Electronics & Communication Engineering, BVRIT, Narsapur, Telangana

ABSTRACT

This paper presents a low power, high gain, low area low pass filter design. The pre-processing block in this filter is the two-stage operational amplifier which is designed using the DTMOSFETS. This filter is operated at very low supply voltages of +0.2V.The PMOS input differential pairs are used to enhance the driving capability of the op-amp. input stage of the op-amp is the differential amplifier in which the inputs are provided to the two PMOS transistors. The second stage is the gain stage in which common source amplifier is used. The design parameter values are determined which optimize an objective feature satisfying specifications or constraints. The low pass filter is designed with a cut-off frequency of 100-HZ and a resistance of 10ohms, which occupies more layout area. In order to reduce the layout area the low pass filter is designed using the switched capacitor. The circuit is implemented with a supply voltage of 0.4V in 0.9-um technology, with a power consumption of 300nW and the simulations are performed using HSPICE simulator and layouts are designed using CUSTOM DESIGNER tool.

KEYWORDS

DTMOS, Switched-capacitor, Low pass filter.

Original Source URL :

http://aircconline.com/vlsics/V7N6/7616vlsi03.pdf

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