Wednesday, 27 April 2022

The importance of convolutional codes is well established. They are widely used to encode digital data before transmission through noisy or error-prone communication channels to reduce occurrence of errors and memory. This paper presents novel decoding technique, memoryless Hybrid Register Exchange with simulation and FPGA implementation results. It requires single register as compared to Register Exchange Method (REM) & Hybrid Register Exchange Method (HREM); therefore the data trans-fer operations and ultimately the switching activity will get reduced.

KEYWORDS

Traceback method, Register Exchange Method, Hybrid Register Exchange Method, Memoryless HREM.

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics04.pdf

https://airccse.org/journal/vlsi/vol2.html

Tuesday, 19 April 2022

International Journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

http://airccse.org/journal/vlsi/vlsics.html

Scope & Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include, but are not limited to, the following:

* Design

* VLSI Circuits

* Computer-Aided Design (CAD)

* Low Power and Power Aware Design

* Testing, Reliability, Fault-Tolerance

* Emerging Technologies

* Post-CMOS VLSI

* VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

* Nano Electronics, Molecular, Biological and Quantum Computing

* Intellectual Property Creating and Sharing

* Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through E-Mail: vlsics@aircconline.com or through Submission System. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates:

· Submission Deadline : April 23, 2022

· Notification : May 23, 2022

· Final Manuscript Due : May 31, 2022

· Publication Date : Determined by the Editor-in-Chief

Contact Us

Here's where you can reach us: vlsicsjournal@airccse.org or vlsics@aircconline.com or vlsicsjournal@yahoo.com

Academia: https://independent.academia.edu/VJournal

Google scholar: https://scholar.google.co.in/citations?user=ZdE-aVMAAAAJ

FB: https://www.facebook.com/vlsics.journal

Twitter: https://twitter.com/Journal_VLSICS

Thursday, 14 April 2022

Call for Research Papers! ICDIPV 2022!

11th International Conference on Digital Image Processing and Vision (ICDIPV 2022)

July 23~24, 2022, Toronto, Canada

https://www.itcse2022.org/icdipv/index

Submission Deadline : April 16, 2022

Submission System: https://www.itcse2022.org/submission/index.php

Contact Us

Here's where you can reach us : icdipv@itcse2022.org or icdipconf@yahoo.com

#Humanbiometrics #Securitysystems #Imagescanning #Retrieval #Storage #Visualization #Transmission

Wednesday, 6 April 2022

A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic

P. Prasad Rao and K. Lal Kishore, JNTU-Hyderabad, India

Abstract

Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.

Keywords

ADC, 1.5 bit stage, CMFB, Pipeline, Redundancy bit removal algorithm

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics03.pdf

https://airccse.org/journal/vlsi/vol2.html

#Design #VLSI #Lowpower #Reliability #Communications #Security #Sensornetworks

Thursday, 31 March 2022

Test Generation for Analog and Mixed-Signal Circuits Using Hybrid System Models

Tarik NAHHAL1 and Thao Dang2, 1Hassan II University, Morocco and 2VERIMAG, France

ABSTRACT

In this paper we propose an approach for testing time-domain properties of analog and mixed-signal circuits. The approach is based on an adaptation of a recently developed test generation technique for hybrid systems and a new concept of coverage for such systems. The approach is illustrated by its application to some benchmark circuits.

KEYWORDS

Hybrid System, Formal Methods in Conformance Testing, Analog and Mixed-Signal Circuit.

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics02.pdf

https://airccse.org/journal/vlsi/vol2.html

#research #VLSI #Embeddedsystem #Electronics #CMOSTechnologies

Wednesday, 23 March 2022

A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

Mouna Karmani*, Chiraz Khedhiri*, Belgacem Hamdi* & Brahim Bensalem**

*Electronics and Microelectronics Laboratory, Monastir, Tunisia

**Embedded and Communication Group, Intel Corporation, Chandler, AZ, USA

Abstract:

In this paper, we propose a simulation-before-test (SBT) fault diagnosis methodology based on the use of a fault dictionary approach. This technique allows the detection and localization of the most likely defects of open-circuit type occurring in Complementary Metal–Oxide–Semiconductor (CMOS) analog integrated circuits (ICs) interconnects. The fault dictionary is built by simulating the most likely defects causing the faults to be detected at the layout level. Then, for each injected fault, the spectre’s frequency responses and the power consumption obtained by simulation are stored in a table which constitutes the fault dictionary. In fact, each line in the fault dictionary constitutes a fault signature used to identify and locate a considered defect. When testing, the circuit under test is excited with the same stimulus, and the responses obtained are compared to the stored ones. To prove the efficiency of the proposed technique, a full custom CMOS operational amplifier is implemented in 0.25 µm technology and the most likely faults of opencircuit type are deliberately injected and simulated at the layout level.

Keywords:

Analog testing, fault diagnosis, fault dictionary, Fast Fourier Transform (FFT), power consumption, opencircuit fault.

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics01.pdf

https://airccse.org/journal/vlsi/vol2.html