A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic

P. Prasad Rao and K. Lal Kishore, JNTU-Hyderabad, India

 Abstract

Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock. 

Keywords

ADC, 1.5 bit stage, CMFB, Pipeline, Redundancy bit removal algorithm

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics03.pdf

https://airccse.org/journal/vlsi/vol2.html

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