Design of Reversible Sequential Circuit Using Reversible Logic Synthesis

Md. Belayet Ali , Md. Mosharof Hossin and Md. Eneyat Ullah

Department of Computer Science and Engineering, Mawlana Bhashani Science and Technology University, Santosh, Tangail-1902, Bangladesh

Abstract

Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.

Keywords

Reversible logic, Reversible gate, Power dissipation, Flip-Flop, Garbage, BME gate.

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics04.pdf

https://airccse.org/journal/vlsi/vol2.html

FPGA Implementation of Deblocking Filter Custom Instruction Hardware on NIOS - II Based SOC

Bolla Leela Naresh1, N.V.Narayana Rao 2 and Addanki Purna Ramesh3

Department of ECE, Sri Vasavi Engg College, Tadepalligudem, West Godavari (dt), Andhra Pradesh, India

ABSTRACT

This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been extended. Deblocking filter new instruction added to the processor that are implemented in hardware and interfaced to the NIOSII processor. New instruction added to the processor to boost the performance of the deblocking filter algorithm. Use of custom instructions the implemented tasks have been accelerated by 5.88%. The benefit of the speed is obtained at the cost of very small hardware resources.

KEYWORDS

Deblocking filter, SOC, NIOS-II soft processor, FPGA 

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics03.pdf

https://airccse.org/journal/vlsi/vol2.html

A New Design Technique of Reversible BCD Adder Based on NMOS with Pass Transistor Gates

Md. Sazzad Hossain1, Md. Rashedul Hasan Rakib1, Md. Motiur Rahman1, A. S. M. Delowar Hossain1 and Md. Minul Hasan2

1Department of Computer Science and Engineering, Mawlana Bhashani Science & Technology University, Santosh, Tangail-1902, Bangladesh

2Amader Ltd, 5B Union Erin, 9/1 North Dhanmondi, Kalabagan, Dhaka, Bangladesh.

ABSTRACT

In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.

KEYWORDS

CMOS, Feynman gates, Fredkin gate, NMOS & pass transistor. 

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics02.pdf

https://airccse.org/journal/vlsi/vol2.html

11th International Conference on Digital Image Processing and Pattern Recognition (DPPR 2021)

11^th International Conference on Digital Image Processing and Pattern Recognition (DPPR 2021)

November 27 ~ 28, 2021, Dubai, UAE

https://cndc2021.org/dppr/index

Scope

11^th International Conference on Digital Image Processing and Pattern Recognition (DPPR 2021) is a forum for presenting new advances and research results in the fields of Digital Image Processing. The Conference will bring together leading researchers, engineers and scientists in the domain of interest from around the world. The scope of the conference covers all theoretical and practical aspects of the Digital Image Processing & Pattern Recognition, from basic research to development of application.

Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences.

Topics of Interest

·         Image acquisition & Medical Image Processing

·         Pattern Recognition and Analysis

·         Visualization

·         Image Coding and Compression

·         Face Recognition & Super-resolution Imaging

·         Image Segmentation

·         Face Recognition

·         3D and Surface Reconstruction

·         3D and Stereo Imaging

·         Analog and Mixed Signal Processing

·         Application & Others

·         Applications (Biomedical, Bioinformatics, Genomic, Seismic, Radar, Sonar, Remote Sensing, Positioning, etc.)

·         Array Signal Processing

·         Audio/Speech Processing and Coding

·         Digital & Mobile Signal Processing

·         Statistical & Optical Signal Processing

·         Data Mining Techniques

·         Motion Detection

·         Content-based Image retrieval

·         Video Signal Processing

·         Watermarking

·         Detection and Estimation of Signal Parameters

·         Signal Identification

·         Nonlinear Signals and Systems

·         Time-Frequency Signal Analysis

·         Signal Reconstruction

·         Spectral Analysis

·         Filter Design and Structures

·         FIR, IIR, Adaptive Filters

·         Signal Noise Control

·         Multiple Filtering and Filter Banks

·         Biomedical Imaging Technologies

·         Biometrics and Pattern Recognition

·         Cognitive and Biologically-Inspired Vision

·         Color and Texture

·         Communication Signal processing

·         Distributed Source Coding

·         Computer Communication and Networks

·         Computer Vision & VR

·         Constraint Processing

·         Document Recognition

·         DSP Implementation and Embedded Systems

·         Face and Gesture

·         Hardware Implementation for Signal Processing

·         Higher Order Spectral Analysis

·         Illumination and Reflectance Modeling

·         Image and Video Retrieval

·         Image Processing & Understanding

·         Image-Based Modeling

·         Internet Signal Processing

·         Knowledge Representation and High-Level Vision

·         Medical Image Analysis

·         Motion and Tracking Stereo and Structure from Motion

·         Multidimensional Signal Processing

·         Multi-view Geometry

·         Neural Networks and Genetic Algorithms

·         Object Detection, Recognition and Categorization

·         Pattern Recognition in New Modalities

·         PDE for Image Processing

·         Performance Evaluation

·         Radar Signal Processing

·         Remote Sensing

·         Segmentation

·         Sensor Array and Multi-Channel Processing

·         Shape Representation

·         Signal Processing Education

·         Sonar Signal Processing and Localization

·         Speech, Audio and Music Processing

·         Statistic Learning & Pattern Recognition

·         Text Processing

·         Time-Frequency/Time-Scale Analysis

·         Video Analysis and Event Recognition

·         Video Compression & Streaming

·         Video Surveillance and Monitoring

Paper Submission

Authors are invited to submit papers through the conference Submission System by November 14, 2021 (Final Call). Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by Computer Science Conference Proceedings in Computer Science & Information Technology (CS & IT) series (Confirmed).

Selected papers from DPPR 2021, after further revisions, will be published in the special issue of the following journals.

·         Signal & Image Processing : An International Journal (SIPIJ)

·         International Journal of VLSI Design & Communication Systems (VLSICS)

·         International Journal of Embedded Systems and Applications (IJESA)

·         International Journal on Organic Electronics (IJOE)

·         Information Technology in Industry (ITII)^New - ESCI(WOS) Indexed

 

Important Dates

·         Submission Deadline: November 14, 2021 (Final Call)

·         Authors Notification: November 22, 2021

·         Registration & Camera-Ready Paper Due: November 24, 2021

 

Contact Us

 

Here's where you can reach us: dppr@cndc2021.org (or) dpprc@yahoo.com

For more details, please visit: https://cndc2021.org/dppr/index

 

Paper Submission Link: https://cndc2021.org/submission/index.php

 

A New Full Adder Cell for Molecular Electronics

Mehdi Ghasemi1,2, Mohammad Hossein Moaiyeri1,2, and Keivan Navi1,2

1Faculty of Electrical and Computer Engineering, Shahid Beheshti University G.C., Tehran, Iran.

2Nanotechnology and Quantum Computing Lab, Shahid Beheshti University G.C., Tehran, Iran.

ABSTRACT

Due to high power consumption and difficulties with minimizing the CMOS transistor size, molecular electronics has been introduced as an emerging technology. Further, there have been noticeable advances in fabrication of molecular wires and switches and also molecular diodes can be used for designing different logic circuits. Considering this novel technology, we use molecules as the active components of the circuit, for transporting electric charge. In this paper, a full adder cell based on molecular electronics is presented. This full adder is consisted of resonant tunneling diodes and transistors which are implemented via molecular electronics. The area occupied by this kind of full adder would be much times smaller than the conventional designs and it can be used as the building block of more complex molecular arithmetic circuits.

KEYWORDS

Logic circuits, full adder, nanotechnology, molecular electronics, resonant tunneling diode (RTD)

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics01.pdf

https://airccse.org/journal/vlsi/vol2.html

Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Universal Logic Gates

K. Ragini1, M. Satyam2 and B. C. Jinaga3 , 1G. Narayanamma Institute of Technology & Science, India, 2International Institute of Information Technology, India and 3Jawaharlal Nehru Technology University, India

ABSTRACT

In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages. 

The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..

The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.

KEYWORDS

Sub- threshold, Dynamic threshold MOS Inverter, Propagation delay, Noise-margin, Variable threshold MOS Inverter, Power dissipation.

Original Source URL: https://aircconline.com/vlsics/V1N1/0310vlsics4.pdf

https://airccse.org/journal/vlsi/vol1.html

Arithmetic Operations in Multi-Valued Logic

Vasundara Patel K. S1 and K. S Gurumurthy2, 

1Vishweshwaraiah Technological University, India and 2UVCE, Bangalore, India

Abstract

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.

KEYWORDS

Multiple-valued logic, Quaternary logic, Modulo-n addition and multiplication, Galois addition and multiplication.

Original Source URL: https://aircconline.com/vlsics/V1N1/0310vlsics3.pdf

https://airccse.org/journal/vlsi/vol1.html