International journal of VLSI design & Communication Systems (VLSICS)

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International journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527 (print)

Webpage URL:

https://airccse.org/journal/vlsi/vlsics.html

Submission Deadline: November 30, 2024

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Here's where you can reach us: jvlsics@gmail.com (or) vlsicsjournal@airccse.org (or) vlsics@aircconline.com

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International journal of VLSI design & Communication Systems (VLSICS)

International journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527 (print)

Webpage URL: http://airccse.org/journal/vlsi/vlsics.html

Design of Low Power Medical Device

Wei Cai and Frank Shi, University of California, USA

Abstract

This paper describes the design of an MMIC phase shifter which can be used in a 4-channel 26-28 GHZ transmitter IC. The MMIC phase shifter is used for 5G RF front Ended applications. MMICs usually include power amplifiers with 4-bit digital phase shifters to make the phase adjustable. The whole design was used for the transmit chain of a mobile device and in a base-station. Future topology will continue to be improved.

Keywords

Doherty Power Amplifier, MMIC, phase shifter 

Original Source URL: https://aircconline.com/vlsics/V8N2/8217vlsi01.pdf

Volume URL: https://airccse.org/journal/vlsi/vol8.html

International journal of VLSI design & Communication Systems (VLSICS)

International journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527 (print)

Webpage URL: http://airccse.org/journal/vlsi/vlsics.html

Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effect Transistors in 32 Nanometer Technology

Ali Ghorbani and Ghazaleh Ghorbani, Islamic Azad University, Iran

Abstract

Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs). Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer technology in Different values of temperature and VDD.

Keywords

Low power circuit; Carbon Nanotube Filed Effect Transistors; Nano Transistors; Full Adder

Original Source URL: https://aircconline.com/vlsics/V5N5/5514vlsi01.pdf

Volume URL: https://airccse.org/journal/vlsi/vol5.html

International journal of VLSI design & Communication Systems (VLSICS)

International journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527 (print)

Webpage URL: https://airccse.org/journal/vlsi/vlsics.html

Survey on Power Optimization Techniques for Low PowerVLSI Circuitsin Deep Submicron Technology

T. Suguna and M. Janaki Rani, Dr.M.G. R Educational and Research Institute, India

Abstract

CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.

Keywords

leakage power, low power, voltage scaling, power gating, transistor stacking, adiabatic logic

Original Source URL: https://aircconline.com/vlsics/V9N1/9118vlsi01.pdf

Volume URL: https://airccse.org/journal/vlsi/vol9.html

International journal of VLSI design & Communication Systems (VLSICS)

International journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527 (print)

Webpage URL: https://airccse.org/journal/vlsi/vlsics.html

Towards Temperature Insensitive Nanoscale CMOS Circuits with Adaptively Regulated Voltage Power Supplies

Ming Zhu1, Yingtao Jiang1, Mei Yang1 and Xiaohang Wang2, 1University of Nevada Las Vegas, USA and 2South China University of Technology, China

ABSTRACT

In this paper, we show that the temperature-induced performance drop seen in nanoscale CMOS circuitscan be tackled by powering the circuits with adaptively regulated voltage power supplies. Essentially, when temperature rises, the supply voltage will be bumped up to offset otherwise performance degradation. To avoid thermal over-drift as chip temperature exceeds its operation range, a voltage limiteris integrated into the proposed power supply to cap the supply voltage. Using this proposed adaptive voltage source to power individual CMOS logic gates and/or subsystems will free the chips from using expensive high-precision temperature sensors for thermal management and performance tuning. Experiments on various benchmark circuits, which are implemented with a 45nm CMOS technology, have confirmed that the circuit delay variation can be reduced to 15%~30% over a wide temperature range (0℃ to 90℃), a sharp contrast to the large delay variations(50%~75%)observed in most IC designs where a constant power supply is employed.

KEYWORDS

High performance VLSI circuits; temperature-insensitive; voltage control; power supply.

Original Source URL: https://aircconline.com/vlsics/V8N3/8317vlsi01.pdf

Volume URL: https://airccse.org/journal/vlsi/vol8.html