International Journal Of VLSI Design & Communication Systems ( VLSICS ): April 2021

A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.

Keywords

AES pipelining, Key pipelining, Search Based Memory, VLSI.

Original Source URL: https://aircconline.com/vlsics/V1N4/1210vlsics05.pdf

http://airccse.org/journal/vlsi/vol1.html

Sunday, 18 April 2021

Call for Papers - International Journal of VLSI design & Communication Systems ( VLSICS )

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

http://airccse.org/journal/vlsi/vlsics.html

Scope & Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include, but are not limited to, the following:

* Design

* VLSI Circuits

* Computer-Aided Design (CAD)

* Low Power and Power Aware Design

* Testing, Reliability, Fault-Tolerance

* Emerging Technologies

* Post-CMOS VLSI

* VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

* Nano Electronics, Molecular, Biological and Quantum Computing

* Intellectual Property Creating and Sharing

* Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through E-Mail: vlsicsjournal@airccse.org or through Submission System. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates:

· Submission Deadline : April 24, 2021

· Notification : May 24, 2021

· Final Manuscript Due : May 31, 2021

· Publication Date : Determined by the Editor-in-Chief

Contact Us

Here's where you can reach us : vlsicsjournal@airccse.org or vlsicsjournal@yahoo.com

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Thursday, 15 April 2021

Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Low Power applications

Shanthala S1, Cyril Prasanna Raj P2, Dr. S.Y.Kulkarni3

1Research Scholar in EC Research Centre, NMAMIT, Nitte

ABSTRACT

Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.

KEYWORD

DSP, MAC, CMOS, Pipeline, Static and Dynamic

Original Source URL: https://aircconline.com/vlsics/V1N4/1210vlsics04.pdf

http://airccse.org/journal/vlsi/vol1.html

Thursday, 8 April 2021

Single Electron Transistor: Applications & Problems

Om Kumar and Manjit Kaur

VLSI-ES Department, Centre for Development of Advanced Computing, Mohali, India

ABSTRACT

The goal of this paper is to review in brief the basic physics of nanoelectronic device single-electron transistor [SET] as well as prospective applications and problems in their applications. SET functioning based on the controllable transfer of single electrons between small conducting "islands". The device properties dominated by the quantum mechanical properties of matter and provide new characteristics coulomb oscillation, coulomb blockade that is helpful in a number of applications. SET is able to shear domain with silicon transistor in near future and enhance the device density. Recent research in SET gives new ideas which are going to revolutionize the random access memory and digital data storage technologies.

Keywords

Nanoelectronics; Single-electron transistor; Coulomb blockade, Coulomb oscillation, Quantum dot

Original Source URL: https://aircconline.com/vlsics/V1N4/1210vlsics03.pdf

http://airccse.org/journal/vlsi/vol1.html