VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM

VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM

Bijal Thakkar1 and V Jayashree2

1Research Scholar, Electronics Dept., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji, Maharashtra, India.

2Professor, Electronics Dept ., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji, Maharashtra, India.

ABSTRACT

Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of its high performance and high-frequency operation without using complex bridges. AXI is also backwardcompatible with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the other protocol but it is possible in AXI because it contains different write address and data channels and AXI also supports out of order transfer based on the transaction ID which is generated at the start of the transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification Methodology (UVM).The signaling of the five channels such as write address, write data, write response, read address, read data channel of AXI protocol are considered for verification. According to the AXI protocol,the signals of these channels are driven to the interconnect and results are observed for single master and single slave. The driver logic has been implemented and verified successfully according to AXI

protocol using the Rivera Pro. The results observed for single master and single slave have shown the correctness of AMBA-AXI design in Verilog.

KEYWORDS

AMBA(Advance Microcontroller Bus Architecture),AXI(Advanced Extensible Interface),UVM(Universal Verification Methodology),channel.

Original Source URL : https://aircconline.com/vlsics/V9N3/9318vlsi03.pdf

http://airccse.org/journal/vlsi/vol9.html

VLSI DESIGN OF AMBA BASED AHB2APB BRIDGE

VLSI DESIGN OF AMBA BASED AHB2APB BRIDGE

Aparna Kharade1 and V. Jayashree2

1Research Scholar, Electronics Dept., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji, Maharashtra, India.

2Professor, Electronics Dept ., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji, Maharashtra, India.

ABSTRACT

The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for highperformance buses to communicate with low-power devices. In the AMBA Advanced High Performance bus (AHB) a system bus is used to connect a processor, a DSP, and high-performance memory controllers where as the AMBA Advanced Peripheral Bus (APB) is used to connect (Universal Asynchronous Receiver Transmitter) UART. It also contains a Bridge, which connects the AHB and APB buses. Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way. So AHB2APB bridge is designed, implemented using VERILOG tool and tested using Verilog testbench and is reported in this paper. A synthesizable RTL code of a complex interface bridge between AHB and APB is developed and known as AHB2APB Bridge. The simulated AHB2APB Bridge results are promising and can be further tested for its verstality by writing a verification program using UVM in future.

KEYWORDS

AMBA; AHB2APB; SOC; VERILOG; XILINX;

Original Source URL : https://aircconline.com/vlsics/V9N3/9318vlsi02.pdf

http://airccse.org/journal/vlsi/vol9.html

IMPLEMENTATION OF LOW POWER ADIABATIC SRAM

IMPLEMENTATION OF LOW POWER ADIABATIC SRAM

Savitha S M1, H P Rajani2 and Shivaling M Hunagund3

1Department of Electronics and Communication, Visvesvaraya Technological University, Belagavi, Karnataka

2HOD of Department of Telecommunication

3Asst Prof. of Department of Electronics and Communication

ABSTRACT

In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.

KEYWORDS

SRAM, Adiabatic, CMOS, Stepwise Charging, SNM and Process variations.

Original Source URL : https://aircconline.com/vlsics/V9N3/9318vlsi01.pdf

http://airccse.org/journal/vlsi/vol9.html