MINIMALLY BUFFERED ROUTER USING WEIGHTED DEFLECTION ROUTING FOR MESH NETWORK ON CHIP

Simi Zerine Sleeba and Mini M.G.

Department of Electronics Engineering, Government Model Engineering College,

Cochin University of Science and Technology Kochi, India

ABSTRACT

The scalability, modularity and massive parallelism exhibited by Network on chip(NoC) interconnects make them highly suitable for the inter core communication framework of multiprocessor system-on-chip (MPSoC) designs. Routers play the most vital role in transferring flits through the network, hence efficient microarchitecture and cost effective routing algorithms are highly essential for modern NoC routers. Elimination of buffers and deflection routing help to achieve energy and area efficiency of these routers. The advantages of bufferless and buffered designs can be combined by using a minimum number of side buffers to store a fraction of deflection flits in the router. In this paper, we propose a routing algorithm based on weighted deflection of flits for minimally buffered deflection routers. Evaluations on 4x4 and 8x8 mesh NoC using synthetic workloads as well as benchmark applications demonstrate that deflection rate and average network latency are significantly reduced in comparison with the state of the art NoC routers. Performance analysis of the newly proposed algorithm shows that the network saturation point improves by 26% compared to earlier designs in this domain.

KEYWORDS

Network on Chip, Deflection routing, Minimal buffering, Average Latency

ORIGINAL SOURCE URL: http://aircconline.com/vlsics/V6N3/6315vlsi06.pdf

VOLUME LINK: http://airccse.org/journal/vlsi/vol6.html