Design and Implementation A different Architectures of mixcolumn in FPGA

Design and Implementation A different Architectures of mixcolumn in FPGA

Sliman Arrag1, Abdellatif Hamdoun2, Abderrahim Tragha 3 and Salah eddine Khamlich 4

1Department of Electronics and treatment of information UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco

2Department of Electronics and treatment of information UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco

3Department of computing and Mathematics UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco

4 Department of Electronics and treatment of information UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco

ABSTRACT

This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.

KEYWORDS:

AES, Mixcolumn , FPGA, VHDL code, encryption

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics02.pdf

http://airccse.org/journal/vlsi/vol3.html