NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITS

Rajani H.P.1 and Srimannarayan Kulkarni2

1Department of Telecommunication Engineering, KLESs College of Engineering and Technology, Belgaum, India

2Principal, M.S. Ramaiah Institute of Technology, Bengaluru, India

ABSTRACT

Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies. 

KEYWORDS

Leakage power, sleep transistor, power gating, average power, state retention

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics08.pdf

http://airccse.org/journal/vlsi/vol3.html

Design of Low Power Sigma Delta ADC

Design of Low Power Sigma Delta ADC

1Mohammed Arifuddin Sohel, 2K. Chenna Kesava Reddy, 3Syed Abdul Sattar

1ECED, Muffakham Jah College of Engineering and Technology, Hyderabad, A.P.

2Principal, TKR College of Engineering, Meerpet, Hyderabad, A.P.

3Professor, ECED, Royal Institute of Technology and Sciences, Chevella, A.P.

ABSTRACT

A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a total power 1.96mW.

KEYWORDS

Discrete Time Sigma Delta Modulation, Low Power design, Oversampling, CIC Decimation Filter

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics07.pdf

http://airccse.org/journal/vlsi/vol3.html

Improved Algorithm for Throughput Maximization in MC-CDMA

Improved Algorithm for Throughput Maximization in MC-CDMA

Hema Kale1, C.G. Dethe2 and M.M. Mushrif3

1ETC Department , Jhulelal Institute of Technology Nagpur , India.

2ECE Department, Priyadarshni Institute of Engineering and Technology, Nagpur , India.

3ETC Department, Yashwantrao Chavan College of Engineering, Nagpur, India

ABSTRACT

The Multi-Carrier Code Division Multiple Access (MC-CDMA) is becoming a very significant downlink multiple access technique for high-rate data transmission in the fourth generation wireless communication systems. By means of efficient resource allocation higher data rate i.e. throughput can be achieved. This paper evaluates the performance of group (subchannel) allocation criteria employed in downlink transmission, which results in throughput maximization. Proposed algorithm gives the modified technique of sub channel allocation in the downlink transmission of MC-CDMA systems. Simulation are carried out for all the three combining schemes, results shows that for the given power and BER proposed algorithm comparatively gives far better results .

KEYWORDS

SCS, MC-CDMA, UWB, SNR, BER, ACA, APA 

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics05.pdf

http://airccse.org/journal/vlsi/vol3.html

FPGA IMPLEMENTATION OF EFFICIENT VLSI ARCHITECTURE FOR FIXED POINT 1-D DWT USING LIFTING SCHEME

FPGA IMPLEMENTATION OF EFFICIENT VLSI ARCHITECTURE FOR FIXED POINT 1-D DWT USING LIFTING SCHEME

Durga Sowjanya1, K N H Srinivas2 and P Venkata Ganapathi3

1Research fellow, Sri Vasavi Engineering College, Tadepalligudem

2Head of the department in Sri Vasavi Engineering College, Tadepalligudem

3Venkata Ganapathi Puppala, Quartics Technologies Pvt Ltd, Pune

ABSTRACT

In this paper, a scheme for the design of area efficient and high speed pipeline VLSI architecture for the computation of fixed point 1-d discrete wavelet transform using lifting scheme is proposed. The main focus of the scheme is to reduce the number and period of clock cycles and efficient area with little or no overhead on hardware resources. The fixed point representation requires less hardware resources compared with floating point representation. The pipelining architecture speeds up the clock rate of DWT and reduced bit precision reduces the area required for implementation. The architecture has been coded in verilog HDL on Xilinx platform and the target FPGA device used is Virtex-II Pro family, XC2VP7- 7board. The proposed scheme requires the least computing time for fixed point 1-D DWT and achieves the less area for implementation, compared with other architectures. So this architecture is realizable for real time processing of DWT computation applications. 

KEYWORDS

Discrete wavelet transform (DWT), Lifting based scheme, field-programmable gate-array (FPGA), pipeline architecture, reduced bit precision, fixed point, VLSI architecture

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics04.pdf

http://airccse.org/journal/vlsi/vol3.html

DELAY ERROR WITH META-STABILITY DETECTION AND CORRECTION USING CMOS TRANSMISSION LOGIC

DELAY ERROR WITH META-STABILITY DETECTION AND CORRECTION USING CMOS TRANSMISSION LOGIC

Bhawna Kankane1, Sandeep Sharma2 , and Navaid Zafar Rizvi3

1,2,3Department of Electronics Engineering, Gautam Buddha University, Greater Noida, India

ABSTRACT

The new technologies are giving the advance systems which are capable to perform multiple operations simultaneously. This all is possible by the scaling technology where the overall chip size get reduced but due to manufacturing and fabrication defects, certain design uncertainty arises thereby affecting the transistor performance by timing related effect. The robust circuit where sufficient margins are given sometime is nothing but a wastage of power to overcome this, hybrid technique called Razor was innovated which scaled the voltage dynamically and automatically detect and correct the timing related defects. This paper proposed a new design for the razor flip flop with CMOS transmission logic. The traditional design used the dynamic logic approach which has the drawback of threshold voltage attenuation which is removed by CMOS transmission logic and the transparency of the logic data at input and output is highly achieved. The overall purpose for such design is to reduce the power and delay of the circuit which is reduced by 0.6mW and 12.11ns respectively and thus increased the overall performance. The complexity of

the circuit is also reduced. The analyses of the circuit is done using Cadence virtuoso tool with 45n technology.

KEYWORDS

Razor, CMOS transmission logic, meta-stability detector, DVS 

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics03.pdf

http://airccse.org/journal/vlsi/vol3.html

Design and Implementation A different Architectures of mixcolumn in FPGA

Design and Implementation A different Architectures of mixcolumn in FPGA

Sliman Arrag1, Abdellatif Hamdoun2, Abderrahim Tragha 3 and Salah eddine Khamlich 4

1Department of Electronics and treatment of information UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco

2Department of Electronics and treatment of information UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco

3Department of computing and Mathematics UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco

4 Department of Electronics and treatment of information UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco

ABSTRACT

This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.

KEYWORDS:

AES, Mixcolumn , FPGA, VHDL code, encryption

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics02.pdf

http://airccse.org/journal/vlsi/vol3.html