VLSI IMPLEMENTATION OF AREA EFFICIENT 2-PARALLEL FIR DIGITAL FILTER

VLSI IMPLEMENTATION OF AREA EFFICIENT 2-PARALLEL FIR DIGITAL FILTER

L kholee phimu and Manoj kumar

Department of Electronic and Communication Engineering, NIT Manipur, India

ABSTRACT

This paper aims to implement an area efficient 2-parallel FIR digital filter. Xilinx 14.2 is used for synthesis and simulation. Parallel filters are designed by using VHDL. Comparison among primary 2–parallel FIR digital filter and area efficient 2-parallel FIR digital filter has been done. Since adders are less weight in term of silicon area, compare to multipliers. Therefore multipliers are replaced with adders for reducing area and speed of the filter. 2-parallel FIR filter is used in digital signal processing (DSP) application.

KEYWORDS

Finite impulse response (FIR), Booth multiplier, Carry-look-ahead adder (CLA), Digital Signal Processing (DSP), Parallel FIR, Very Large Scale Integration (VLSI)

Original Source URL :

http://aircconline.com/vlsics/V7N6/7616vlsi02.pdf

For More Details :

http://airccse.org/journal/vlsi/vlsics.html