BUILT-IN SELF-TEST ARCHITECTURE USING LOGIC MODULE

BUILT-IN SELF-TEST ARCHITECTURE USING LOGIC MODULE

Sakshi Shrivastava, Sunil Malviya and Neelesh Gupta

Dept. of ECE, Truba College of Science and Technology, Bhopal, M.P., India

ABSTRACT

A Built-in self-test technique constitute a class of algorithms that provide the capability of performing at speed testing with high fault coverage, whereas at the same time they relax the reliance on expensive external testing equipment. Hence, they constitute a striking solution to the problem of testing VLSI devices. BIST techniques are typically classified into offline and online Concurrent BIST performs two modes of operations, test mode and normal mode during test mode the test generator (TG) result is compared with higher order bits and the output is given to comparator circuit. During normal operation mode the inputs to the CUT are driven from the normal inputs. The modified Decoder and SRAM is used to reduce the switching activity thus the dynamic power dissipation can be decrease. The output is verified by response verifier (RV) and the fault is recognizedby using testing. The operating speed is faster while the operation is carried out as parallel process and it is suitable for all the type of IC’s and VLSI circuits.

KEYWORDS

Built-In Self-Test, Design for Testability, Testing.


Original Source URL :

http://aircconline.com/vlsics/V8N4/8417vlsi03.pdf

For More Details :

http://airccse.org/journal/vlsi/vol8.html