DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY

DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY

Silpa Kesav¹, K.S.Nayanathara² and B.K. Madhavi³

^1,2(ECE, CVR College of Engineering, Hyderabad, India)

³(ECE, Sridevi Women’s Engineering College, Hyderabad, India)

ABSTRACT

Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in 45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.

KEYWORDS

Analog-to-Digital Converter, Digital-to-Analog Converter, CMOS, ENOB, SNR and Low power. 

Original Source URL :

http://aircconline.com/vlsics/V8N1/8117vlsi02.pdf

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http://airccse.org/journal/vlsi/vlsics.html