VLSI IMPLEMENTATION OF AREA EFFICIENT 2-PARALLEL FIR DIGITAL FILTER

VLSI IMPLEMENTATION OF AREA EFFICIENT 2-PARALLEL FIR DIGITAL FILTER

L kholee phimu and Manoj kumar

Department of Electronic and Communication Engineering, NIT Manipur, India

ABSTRACT

This paper aims to implement an area efficient 2-parallel FIR digital filter. Xilinx 14.2 is used for synthesis and simulation. Parallel filters are designed by using VHDL. Comparison among primary 2–parallel FIR digital filter and area efficient 2-parallel FIR digital filter has been done. Since adders are less weight in term of silicon area, compare to multipliers. Therefore multipliers are replaced with adders for reducing area and speed of the filter. 2-parallel FIR filter is used in digital signal processing (DSP) application.

KEYWORDS

Finite impulse response (FIR), Booth multiplier, Carry-look-ahead adder (CLA), Digital Signal Processing (DSP), Parallel FIR, Very Large Scale Integration (VLSI)

Original Source URL :

http://aircconline.com/vlsics/V7N6/7616vlsi02.pdf

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http://airccse.org/journal/vlsi/vlsics.html

SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRCUITS

SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRCUITS

Ali T. Shaheen and Saleem M. R. Taha

Department of Electrical Engineering, University of Baghdad, Iraq

ABSTRACT

Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase. Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power saving ranged (from 62.8% to 67%).

KEYWORDS

Dual Threshold Design, Slack Based Genetic Algorithm, Sub-threshold Circuits, Reverse Body Bias, Standby Power 

Original Source URL :

http://aircconline.com/vlsics/V7N6/7616vlsi01.pdf

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DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY

DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY

Silpa Kesav¹, K.S.Nayanathara² and B.K. Madhavi³

^1,2(ECE, CVR College of Engineering, Hyderabad, India)

³(ECE, Sridevi Women’s Engineering College, Hyderabad, India)

ABSTRACT

Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in 45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.

KEYWORDS

Analog-to-Digital Converter, Digital-to-Analog Converter, CMOS, ENOB, SNR and Low power. 

Original Source URL :

http://aircconline.com/vlsics/V8N1/8117vlsi02.pdf

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A PREDICTION METHOD OF GESTURE TRAJECTORY BASED ON LEAST SQUARES FITTING MODEL

A PREDICTION METHOD OF GESTURE TRAJECTORY BASED ON LEAST SQUARES FITTING MODEL

Cai Mengmeng^1,2 Feng Zhiquan^1,2 and Luan Min^1,2

¹School of Information Science and Engineering,

University of Jinan, Jinan, China 250022

²Shandong Provincial Key Laboratory of Network-based Intelligent Computing,

Jinan, China, 250022, P.R.

ABSTRACT

Implicit interaction based on context information is widely used and studied in the virtual scene. In context based human computer interaction, the meaning of action A is well defined. For instance, the right wave is defined turning paper or PPT in context B, And it mean volume up in context C. However, we cannot use the context information when we select the object to be manipulated. In view of this situation, this paper proposes using the least squares fitting curve beam to predict the user's trajectory, so as to determine what object the user’s wants to operate. At the same time, the fitting effects of the three curves were compared, and the curve which is more accord with the hand movement trajectory is obtained. In addition, using the bounding box size control the Z variable to move in an appropriate location. Experimental results show that the proposed in this paper based on bounding box size to control the Z variables get a good effect; by fitting the trajectory of a human hand, to predict the object that the subjects would like to operate. The correct rate is 91%.

KEYWORDS

Least-squares method; dynamic gesture recognition; implicit interaction; edge point sequential extraction; context information 

Original Source URL :

http://aircconline.com/vlsics/V8N1/8117vlsi01.pdf

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http://airccse.org/journal/vlsi/vol8.html

DESIGN OF LOW POWER MEDICAL DEVICE

DESIGN OF LOW POWER MEDICAL DEVICE

Wei Cai¹ and Frank Shi²

¹Department of Electrical Engineering and Computer Science,

University of California, Irvine, USA

²HHS School of Engineering, University of California, Irvine, USA

ABSTRACT

This paper describes the design of an MMIC phase shifter which can be used in a 4-channel 26-28 GHZ transmitter IC. The MMIC phase shifter is used for 5G RF front Ended applications. MMICs usually include power amplifiers with 4-bit digital phase shifters to make the phase adjustable. The whole design was used for the transmit chain of a mobile device and in a base-station.Future topology will continue to be improved.

KEYWORDS

Doherty Power Amplifier, MMIC, phase shifter

Original Source URL :

http://aircconline.com/vlsics/V8N2/8217vlsi01.pdf

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http://airccse.org/journal/vlsi/vlsics.html

TOWARDS TEMPERATURE-INSENSITIVE NANOSCALE CMOS CIRCUITS WITH ADAPTIVELY REGULATED VOLTAGE POWER SUPPLIES

TOWARDS TEMPERATURE-INSENSITIVE NANOSCALE CMOS CIRCUITS WITH ADAPTIVELY REGULATED VOLTAGE POWER SUPPLIES

Ming Zhu¹, Yingtao Jiang¹, Mei Yang¹, Xiaohang Wang²

¹Department of Electrical and Computer Engineering

University of Nevada Las Vegas, Las Vegas, NVUSA 89154

²School of Software, South China University of Technology, Guangzhou, China

ABSTRACT

In this paper, we show that the temperature-induced performance drop seen in nanoscale CMOS circuits can be tackled by powering the circuits with adaptively regulated voltage power supplies. Essentially, when temperature rises, the supply voltage will be bumped up to offset otherwise performance degradation. To avoid thermal over-drift as chip temperature exceeds its operation range, a voltage limiter is integrated into the proposed power supply to cap the supply voltage. Using this proposed adaptive voltage source to power individual CMOS logic gates and/or subsystems will free the chips from using expensive high-precision temperature sensors for thermal management and performance tuning. Experiments on various benchmark circuits, which are implemented with a 45nm CMOS technology, have confirmed that the circuit delay variation can be reduced to 15%~30% over a wide temperature range (0℃ to 90℃), a sharp contrast to the large delay variations (50%~75%)observed in most IC designs where a constant power supply is employed.

KEYWORDS

High performance VLSI circuits; temperature-insensitive; voltage control; power supply. 


Original Source URL :

http://aircconline.com/vlsics/V8N3/8317vlsi01.pdf

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http://airccse.org/journal/vlsi/vlsics.html

BUILT-IN SELF-TEST ARCHITECTURE USING LOGIC MODULE

BUILT-IN SELF-TEST ARCHITECTURE USING LOGIC MODULE

Sakshi Shrivastava, Sunil Malviya and Neelesh Gupta

Dept. of ECE, Truba College of Science and Technology, Bhopal, M.P., India

ABSTRACT

A Built-in self-test technique constitute a class of algorithms that provide the capability of performing at speed testing with high fault coverage, whereas at the same time they relax the reliance on expensive external testing equipment. Hence, they constitute a striking solution to the problem of testing VLSI devices. BIST techniques are typically classified into offline and online Concurrent BIST performs two modes of operations, test mode and normal mode during test mode the test generator (TG) result is compared with higher order bits and the output is given to comparator circuit. During normal operation mode the inputs to the CUT are driven from the normal inputs. The modified Decoder and SRAM is used to reduce the switching activity thus the dynamic power dissipation can be decrease. The output is verified by response verifier (RV) and the fault is recognizedby using testing. The operating speed is faster while the operation is carried out as parallel process and it is suitable for all the type of IC’s and VLSI circuits.

KEYWORDS

Built-In Self-Test, Design for Testability, Testing.


Original Source URL :

http://aircconline.com/vlsics/V8N4/8417vlsi03.pdf

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http://airccse.org/journal/vlsi/vol8.html

SIMULATION OF FIR FILTER BASED ON CORDIC ALGORITHM

SIMULATION OF FIR FILTER BASED ON CORDIC ALGORITHM

Shalini Rai and Rajeev Srivastava

Department of Electronics & Communication,

University of Allahabad, Allahabad (UP)

ABSTRACT

Coordinate Rotation Digital Computer (CORDIC) discovered by Jack E Volder. It is a shift-add operation and iterative algorithm. CORDIC algorithm has wide area for several applications like digital signal processing, biomedical processing, image processing, radar signal processing, 8087 math coprocessor, the HP-35 calculator, Discrete Fourier, Discrete Hartley and Chirp-Z transforms, filtering, robotics, real time navigational system and also in communication systems. In this paper, we discussed about the CORDIC algorithm and CORDIC algorithm based finite impulse response low pass & high pass filter. We have generated the M-code for the CORDIC Algorithm and CORDIC Algorithm based FIR filter with the help of MATLAB 2010a.We also discussed about the frequency response characteristics of FIR filter.

KEYWORDS

CORDIC Algorithm, FIR Filter, MATLAB


Original Source URL :

http://aircconline.com/vlsics/V8N4/8417vlsi02.pdf

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http://airccse.org/journal/vlsi/vol8.html

DESIGN OF QUATERNARY LOGICAL CIRCUIT USING VOLTAGE AND CURRENT MODE LOGIC

DESIGN OF QUATERNARY LOGICAL CIRCUIT USING VOLTAGE AND CURRENT MODE LOGIC

Shweta Hajare and Pravin Dakhole

Research scholar Department of Electronics Engineering,

Yeshwantrao Chavan college of Engg, Nagpur, India

ABSTRACT

In VLSI technology, designers main concentration were on area required and on performance of the device. In VLSI design power consumption is one of the major concerns due to continuous increase in chip density and decline in size of CMOS circuits and frequency at which circuits are operating. By considering these parameter logical circuits are designed using quaternary voltage mode logic and quaternary current mode logic. Power consumption required for quaternary voltage mode logic is 51.78 % less as compared to binary . Area in terms of number of transistor required for quaternary voltage mode logic is 3 times more as compared to binary. As quaternary voltage mode circuit required large area as compared to quaternary current mode circuit but power consumption required in quaternary voltage mode circuit is less than that required in quaternary current mode circuit .

KEYWORDS

Multiple-Valued Logic (MVL), Quaternary voltage mode, Quaternary current mode, MIN, MAX


Original Source URL : 

http://aircconline.com/vlsics/V8N4/8417vlsi01.pdf

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http://airccse.org/journal/vlsi/vol8.html

ZIGBEE TRANSMITTER FOR IOT WIRELESS DEVICES

ZIGBEE TRANSMITTER FOR IOT WIRELESS DEVICES

A.Mounica¹ and G.V.Subbareddy²

¹MTech VLSI Design, Dept of ECE, GRIET Hyderabad, India.

²Associative Professor in Dept of ECE, GRIET Hyderabad, India.

ABSTRACT

The rapid development in wireless networking has been witnessed in past several years, which aimed on high speed and long range applications. There are different protocol standards used for the short range wireless communication namely the Bluetooth, ZigBee, Wimax and Wi-Fi. Among these standards ZigBee is based on IEEE 802.15.4 protocol can meet a wider variety of real industrial needs due to its long-term battery operation and reliability of the mesh networking architecture. The increasing demand for low data rate and low power networking led to the development of ZigBee technology. This technology was developed for Wireless Personal Area Networks (WPAN), directed at control and military applications, where low cost, low data rate, and more battery life were main requirements. This paper presents VerilogHDL simulation of the Top level module (Cyclic Redundancy Check, Bit-to-Symbol block, Symbol-to-Chip block, OQPSK block and Pulse shaping) of the ZigBee transmitter for IoT applications.

KEYWORDS

Cyclic Redundancy Check, Bit-to-Symbol, Symbol-to-Chip, Offset Quadrature Phase Shift Keying Modulator and Pulse Shaping. 

Original Source URL : 

http://aircconline.com/vlsics/V8N5/8517vlsi01.pdf

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http://airccse.org/journal/vlsi/vol8.html

VLSI ARCHITECTURE FOR NANO WIRE BASED ADVANCED ENCRYPTION STANDARD (AES) WITH THE EFFICIENT MULTIPLICATIVE INVERSE UNIT

K.Sandyarani¹ and P. Nirmal Kumar²

¹Research Scholar, Department of ECE, Sathyabama University, Chennai, India

²Associate Professor, Department of ECE, College of Engineering, Guindy, Anna University, Chennai, India

ABSTRACT

Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm. Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural properties. The AES architecture with the enhanced mix column to be proposed with reduced number of transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding the VLSI design environment. The simulation results of the proposed structure are performed with the minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS technology based AES Algorithm is integrated into the backend based chip technology.

KEYWORDS

Advanced Encryption Standard, Sub-Channel, Mix-Column, Verilog A, Complementary metal oxide semiconductor, Nano-technology.

Original Source URL : 

http://aircconline.com/vlsics/V8N6/8617vlsi02.pdf

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http://airccse.org/journal/vlsi/vol8.html

AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPLANTABLE BIO-MEDICAL DEVICES

AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPLANTABLE BIO-MEDICAL DEVICES

Sruthi Nanduru, Santosh Koppa and Eugene John

Department of Electrical and Computer Engineering

University of Texas at San Antonio, Texas, USA

ABSTRACT

The growing demand for energy constrained applications and portable devices have created a dire need for ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold region minimize the energy per operation, thus providing a better platform for energy constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages which can be used for low power implantable bio-medical devices such as pacemakers. To improve the performance of these adders in sub-threshold region, forward body bias technique and multi-threshold transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using 0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to further improve the performance of the adders. The PDP obtained using the forward body biasing technique shows an effective improvement compared to high threshold voltage and multi threshold voltage techniques. The forward biasing technique maintains a balance between delay reduction and increase in average power, thus reducing the power delay product when compared to the other two techniques.

KEYWORDS

Kogge-Stone adder, Bio-Medical, Sub-Threshold, Forward body bias, Multi Threshold

Original Source URL : 

http://aircconline.com/vlsics/V8N6/8617vlsi01.pdf

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http://airccse.org/journal/vlsi/vlsics.html

SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SUBMICRON TECHNOLOGY

SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SUBMICRON TECHNOLOGY

T. Suguna and M. Janaki Rani

Department of Electronics and Communication Engineering,

Dr.M.G. R Educational and Research Institute, Chennai, India

ABSTRACT

CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.

KEYWORDS

leakage power, low power, voltage scaling, power gating, transistor stacking, adiabatic logic.

Original Source URL :

http://aircconline.com/vlsics/V9N1/9118vlsi01.pdf

More Details :

http://airccse.org/journal/vlsi/vlsics.html