SOFTWARE AND HARDWARE DESIGN CHALLENGES IN AUTOMOTIVE EMBEDDED SYSTEM

SOFTWARE AND HARDWARE DESIGN CHALLENGES IN AUTOMOTIVE EMBEDDED SYSTEM

Rajeshwari Hegde1, Geetishree Mishra1, K S Gurumurthy2

1BMS College of Engineering, Bangalore, India

2UVCE, Bangalore, India

ABSTRACT

Modern automotives integrate large amount of electronic devices to improve the driving safety and comfort. This growing number of Electronic Control Units (ECUs) with sophisticated software escalates the vehicle system design complexity. In this paper we explain the complexity of ECUs in terms of hardware and software and also we explore the possibility of Common Object Request Broker Architecture (CORBA) architecture for the integration of add-on software in ECUs. This reduces the complexity of the embedded system in vehicles and eases the ECU integration by reducing the total number of ECUs in the vehicles.

KEYWORDS

AUTOSAR, CORBA, ECU, OEM 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics14.pdf

http://airccse.org/journal/vlsi/vol2.html

AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION SEQUENCES

AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION SEQUENCES

P. Tirumala rao1, P. Siva kumar2, Y.V. Apparao3, Y. Madhu babu4

1&2Dept. of ECE, Vignan institute of information technology, Vizag, Andhra Pradesh, India

3&4Dept. of ECE, GITAM University, Vizag, Andhra Pradesh, India

ABSTRACT

Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an opti-mized and dedicated hardware. The real time implementation places several constraints such as area occupied, power con-sumption, etc. The good design needs optimization of these constraints. This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression se-quence like BPSk, QPSk, 6-PSK and other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.

KEYWORDS

PULSE compression, Ternary sequence, Quaternary sequence, Polyphase sequence,Merit Factor, VLSI architecture, FPGA 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics13.pdf

http://airccse.org/journal/vlsi/vol2.html

DESIGN OF A CMOS BANDGAP REFERENCE WITH LOWTEMPERATURE COEFFICIENT AND HIGH POWER SUPPLY REJECTION PERFORMANCE

DESIGN OF A CMOS BANDGAP REFERENCE WITH LOWTEMPERATURE COEFFICIENT AND HIGH POWER SUPPLY REJECTION PERFORMANCE 

Abhisek Dey1 and Tarun Kanti Bhattacharyya2

Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, West Bengal, India 

ABSTRACT

A high precision temperature compensated CMOS bandgap reference is presented. The proposed circuit employs current-mode architecture that improves the temperature stability of the output reference voltage as well as the power supply rejection when compared to the conventional voltage-mode bandgap referenc. Using only first order compensation the new architecture can generate an output reference voltage of 550mV with a peak-to-peak variation of 400µV over a wide temperature range from -25oC to +100oC which corresponds to a temperature coefficient of 5.8ppm/oC. The output reference voltage exhibits a variation of 2.4mV for supply voltage ranging from 1.6V to 2.0V at typical process corner. A differential cascaded three-stage operational amplifier is included in the bandgap circuit to improve the power supply rejection of the BGR. Simulation result shows that the power supply rejection ratio of the proposed circuit is 79dB from DC up to 1kHz of frequency. The proposed bandgap reference is implemented using UMC 0.18µm CMOS process and it occupies an active layout area of 0.14mm2.

KEYWORDS

BGR, Temperature coefficient, PSRR. 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics12.pdf

http://airccse.org/journal/vlsi/vol2.html

DESIGN AND IMPLEMENTATION OF FPGA BASED SIGNAL PROCESSING CARD

DESIGN AND IMPLEMENTATION OF FPGA BASED SIGNAL PROCESSING CARD

Priya Gupta1 and Deepak Gupta2

1Banasthali University, Rajasthan India

2Alpine System, New Delhi India

ABSTRACT

This paper describes the design of FPGA based signal processing card. An on board real time digital signal processing system is designed using FPGA. The platform can decode process of various kinds of digital and analog signals simultaneously. The design trend in this card is towards small size, high integration and fast real time processing. For the optimum performance a 16 bit 1 MSPS ADC is used which is interfaced with FPGA to make all the data processing onboard in real time. This card can be used in many signal processing based applications like audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications by interfacing several separate board using inbuilt I/O’s, each with a number of input channels that will communicate with each other in real time over a high speed communication link. The resulting images can be displayed directly on LCD or OLED panel displays using I/O’s peripherals. The project introduces many challenging issues, which are being addressed in turn with different prototype designs. These issues are the ADC performance, interfacing the ADCs to the FPGA, implementing the flexible processing  algorithms and high speed interconnection between the boards. 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics11.pdf

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Performance analysis of DWT based OFDM over FFT based OFDM and implementing on FPGA

Performance analysis of DWT based OFDM over FFT based OFDM and implementing on FPGA

Mrs. VEENA M.B1  & Dr. M.N.SHANMUKHA SWAMY2

1Research scholar, ECE Department, SJCE, Mysore, Karnataka, India

2Professor, ECE Department, SJCE, Mysore, Karnataka,India,

ABSTRACT

Growth in technology has led to unprecedented demand for high speed architectures for complex signal processing applications. In 4G wireless communication systems, bandwidth is a precious commodity, and service providers are continuously met with the challenge of accommodating more users with in a limited allocated bandwidth. To increase data rate of wireless medium with higher performance, OFDM (orthogonal frequency division multiplexing) is used. Recently DWT (Discrete wavelet transforms) is adopted in place of FFT (Fast Fourier transform) for frequency translation. Modulation schemes such as 16-QAM, 32-QAM, 64-QAM and 128-QAM (Quadrature amplitude modulation) have been used in the developed OFDM system for both DWT and FFT based model. In this paper we propose a DWT-IDWT based OFDM transmitter and receiver that achieve better performance in terms SNR and BER for AWGN channel. It proves all the wavelet families better over the IFFT-FFT implementation. The OFDM model is developed using Simulink, various test cases have been considered to verify its performance. The DWTOFDM using Lifting Scheme architecture is implemented on FPGA optimizing hardware, speed & cost. The wavelet filter used for this is Daubechies (9, 7) with N=2. The RTL code is written in Verilog-HDL and simulated in Modelsim. The design is then synthesized in Xilinx and implemented on Virtex5 FPGA board and the results were validated using ChipScope.

Keywords:

FFT, DWT, OFDM, BER, Lifting scheme, Simulink 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics10.pdf

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AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIP

AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIP

Rehan Maroofi,1 V. N. Nitnaware,2 and Dr. S. S. Limaye3

1Department of Electronics, Ramdeobaba Kamla Nehru College of Engg, Nagpur, India

2Department of EDT, Ramdeobaba Kamla Nehru College of Engg, Nagpur, India

3Jhulelal Institute of Technology, Nagpur, India

ABSTRACT

Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.

KEYWORDS

Network-on-Chip, System-on-Chip, On-chip routing switch, Scheduler, iSLIP, Synthesis. 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics09.pdf

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PIPELINED ARCHITECTURE OF 2D-DCT, QUANTIZATION AND ZIGZAG PROCESS FOR JPEG IMAGE COMPRESSION USING VHDL

PIPELINED ARCHITECTURE OF 2D-DCT, QUANTIZATION AND ZIGZAG PROCESS FOR JPEG IMAGE COMPRESSION USING VHDL

T.Pradeepthi1 and Addanki Purna Ramesh2

Department of ECE, Sri Vasavi Engg College, Tadepalligudem, West Godavari (dt), Andhra Pradesh, India

ABSTRACT

This paper presents the architecture and VHDL design of a Two Dimensional Discrete Cosine Transform (2D-DCT) with Quantization and zigzag arrangement. This architecture is used as the core and path in JPEG image compression hardware. The 2D- DCT calculation is made using the 2D- DCT Separability property, such that the whole architecture is divided into two 1D-DCT calculations by using a transpose buffer. Architecture for Quantization and zigzag process is also described in this paper. The quantization process is done using division operation. This design aimed to be implemented in Spartan-3E XC3S500 FPGA. The 2D- DCT architecture uses 1891 Slices, 51I/O pins, and 8 multipliers of one Xilinx Spartan-3E XC3S500E FPGA reaches an operating frequency of 101.35 MHz One input block with 8 x 8 elements of 8 bits each is processed in 6604 ns and pipeline latency is 140 clock cycles .

KEYWORDS

JPEG, discrete cosine transform (DCT), quantization, zigzag, FPGA 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics08.pdf

http://airccse.org/journal/vlsi/vol2.html