Tuesday 30 November 2021

Call for Papers - International Journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

http://airccse.org/journal/vlsi/vlsics.html

Scope & Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include, but are not limited to, the following:

* Design

* VLSI Circuits

* Computer-Aided Design (CAD)

* Low Power and Power Aware Design

* Testing, Reliability, Fault-Tolerance

* Emerging Technologies

* Post-CMOS VLSI

* VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

* Nano Electronics, Molecular, Biological and Quantum Computing

* Intellectual Property Creating and Sharing

* Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through E-Mail: vlsics@aircconline.com or through Submission System. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates:

· Submission Deadline : December 04, 2021

· Notification : December 25, 2021

· Final Manuscript Due : December 28, 2021

· Publication Date : Determined by the Editor-in-Chief

Contact Us

Here's where you can reach us: vlsicsjournal@airccse.org or vlsics@aircconline.com or vlsicsjournal@yahoo.com

Wednesday 24 November 2021

Design of Reversible Sequential Circuit Using Reversible Logic Synthesis

Md. Belayet Ali , Md. Mosharof Hossin and Md. Eneyat Ullah

Department of Computer Science and Engineering, Mawlana Bhashani Science and Technology University, Santosh, Tangail-1902, Bangladesh

Abstract

Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.

Keywords

Reversible logic, Reversible gate, Power dissipation, Flip-Flop, Garbage, BME gate.

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics04.pdf

https://airccse.org/journal/vlsi/vol2.html

Wednesday 17 November 2021

FPGA Implementation of Deblocking Filter Custom Instruction Hardware on NIOS - II Based SOC

Bolla Leela Naresh1, N.V.Narayana Rao 2 and Addanki Purna Ramesh3

Department of ECE, Sri Vasavi Engg College, Tadepalligudem, West Godavari (dt), Andhra Pradesh, India

ABSTRACT

This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been extended. Deblocking filter new instruction added to the processor that are implemented in hardware and interfaced to the NIOSII processor. New instruction added to the processor to boost the performance of the deblocking filter algorithm. Use of custom instructions the implemented tasks have been accelerated by 5.88%. The benefit of the speed is obtained at the cost of very small hardware resources.

KEYWORDS

Deblocking filter, SOC, NIOS-II soft processor, FPGA

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics03.pdf

https://airccse.org/journal/vlsi/vol2.html

Thursday 11 November 2021

A New Design Technique of Reversible BCD Adder Based on NMOS with Pass Transistor Gates

Md. Sazzad Hossain1, Md. Rashedul Hasan Rakib1, Md. Motiur Rahman1, A. S. M. Delowar Hossain1 and Md. Minul Hasan2

1Department of Computer Science and Engineering, Mawlana Bhashani Science & Technology University, Santosh, Tangail-1902, Bangladesh

2Amader Ltd, 5B Union Erin, 9/1 North Dhanmondi, Kalabagan, Dhaka, Bangladesh.

ABSTRACT

In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.

KEYWORDS

CMOS, Feynman gates, Fredkin gate, NMOS & pass transistor.

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics02.pdf

https://airccse.org/journal/vlsi/vol2.html

Wednesday 10 November 2021

11th International Conference on Digital Image Processing and Pattern Recognition (DPPR 2021)

11^th International Conference on Digital Image Processing and Pattern Recognition (DPPR 2021)

November 27 ~ 28, 2021, Dubai, UAE

https://cndc2021.org/dppr/index

Scope

11^th International Conference on Digital Image Processing and Pattern Recognition (DPPR 2021) is a forum for presenting new advances and research results in the fields of Digital Image Processing. The Conference will bring together leading researchers, engineers and scientists in the domain of interest from around the world. The scope of the conference covers all theoretical and practical aspects of the Digital Image Processing & Pattern Recognition, from basic research to development of application.

Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences.

Topics of Interest

· Image acquisition & Medical Image Processing

· Pattern Recognition and Analysis

· Visualization

· Image Coding and Compression

· Face Recognition & Super-resolution Imaging

· Image Segmentation

· Face Recognition

· 3D and Surface Reconstruction

· 3D and Stereo Imaging

· Analog and Mixed Signal Processing

· Application & Others

· Applications (Biomedical, Bioinformatics, Genomic, Seismic, Radar, Sonar, Remote Sensing, Positioning, etc.)

· Array Signal Processing

· Audio/Speech Processing and Coding

· Digital & Mobile Signal Processing

· Statistical & Optical Signal Processing

· Data Mining Techniques

· Motion Detection

· Content-based Image retrieval

· Video Signal Processing

· Watermarking

· Detection and Estimation of Signal Parameters

· Signal Identification

· Nonlinear Signals and Systems

· Time-Frequency Signal Analysis

· Signal Reconstruction

· Spectral Analysis

· Filter Design and Structures

· FIR, IIR, Adaptive Filters

· Signal Noise Control

· Multiple Filtering and Filter Banks

· Biomedical Imaging Technologies

· Biometrics and Pattern Recognition

· Cognitive and Biologically-Inspired Vision

· Color and Texture

· Communication Signal processing

· Distributed Source Coding

· Computer Communication and Networks

· Computer Vision & VR

· Constraint Processing

· Document Recognition

· DSP Implementation and Embedded Systems

· Face and Gesture

· Hardware Implementation for Signal Processing

· Higher Order Spectral Analysis

· Illumination and Reflectance Modeling

· Image and Video Retrieval

· Image Processing & Understanding

· Image-Based Modeling

· Internet Signal Processing

· Knowledge Representation and High-Level Vision

· Medical Image Analysis

· Motion and Tracking Stereo and Structure from Motion

· Multidimensional Signal Processing

· Multi-view Geometry

· Neural Networks and Genetic Algorithms

· Object Detection, Recognition and Categorization

· Pattern Recognition in New Modalities

· PDE for Image Processing

· Performance Evaluation

· Radar Signal Processing

· Remote Sensing

· Segmentation

· Sensor Array and Multi-Channel Processing

· Shape Representation

· Signal Processing Education

· Sonar Signal Processing and Localization

· Speech, Audio and Music Processing

· Statistic Learning & Pattern Recognition

· Text Processing

· Time-Frequency/Time-Scale Analysis

· Video Analysis and Event Recognition

· Video Compression & Streaming

· Video Surveillance and Monitoring

Paper Submission

Authors are invited to submit papers through the conference Submission System by November 14, 2021 (Final Call). Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by Computer Science Conference Proceedings in Computer Science & Information Technology (CS & IT) series (Confirmed).

Selected papers from DPPR 2021, after further revisions, will be published in the special issue of the following journals.

· Signal & Image Processing : An International Journal (SIPIJ)

· International Journal of VLSI Design & Communication Systems (VLSICS)

· International Journal of Embedded Systems and Applications (IJESA)

· International Journal on Organic Electronics (IJOE)

· Information Technology in Industry (ITII)^New - ESCI(WOS) Indexed