A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing for Wireless Applications

 S. L. Haridas1 and Dr. N. K. Choudhari2 

1Prof. & Head of E&T Engg., B. D. College of Engg., Sevagram (M.S.), India

 2Principal, Smt. Bhagvati Chaturvedi College of Engg., Nagpur (M.S.), India

 ABSTRACT 

This work proposes the low power implementation of Viterbi Decoder. Majority of viterbi decoder designs in the past use simple Register Exchange or Traceback method to achieve very high speed and low power decoding respectively, but it suffers from both complex routing and high switching activity. Here simplification is made in survivor memory unit by storing only m-1 bits to identify previous state in the survivor path, and by assigning m-1 registers to decision vectors. This approach eliminates unnecessary shift operations. Also for storing the decoded data only half memory is required than register exchange method. In this paper Hybrid approach that combines both Traceback and Register Exchange schemes has been applied to the viterbi decoder design. By using distance properties of encoder we further modified to minimum transition hybrid register exchange method. It leads to lower dynamic power consumption because of lower switching activity. Dynamic power estimation obtained through gate level simulation indicates that the proposed design reduces the power dissipation of a conventional viterbi decoder design by 30%. 

 KEYWORDS 

Traceback method, Register Exchange method, Hybrid Register Exchange method, Minimum Transition Register Exchange Method. 

 Original Source URL: https://aircconline.com/vlsics/V1N4/1210vlsics02.pdf 

http://airccse.org/journal/vlsi/vol1.html