International Journal Of VLSI Design & Communication Systems ( VLSICS ): November 2020

Monday, 30 November 2020

International Journal of VLSI design & Communication Systems ( VLSICS )

International Journal of VLSI design & Communication Systems ( VLSICS )

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

http://airccse.org/journal/vlsi/vlsics.html

Scope & Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include, but are not limited to, the following:

* Design

* VLSI Circuits

* Computer-Aided Design (CAD)

* Low Power and Power Aware Design

* Testing, Reliability, Fault-Tolerance

* Emerging Technologies

* Post-CMOS VLSI

* VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

* Nano Electronics, Molecular, Biological and Quantum Computing

* Intellectual Property Creating and Sharing

* Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through E-Mail: vlsicsjournal@airccse.org or through Submission System. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates:

· Submission Deadline : December 05, 2020

· Notification : January 05, 2021

· Final Manuscript Due : January 13, 2021

· Publication Date : Determined by the Editor-in-Chief

Contact Us

Here's where you can reach us : vlsicsjournal@airccse.org or vlsicsjournal@yahoo.com

Google scholar Link: https://scholar.google.co.in/citations?user=ZdE-aVMAAAAJ

Thursday, 26 November 2020

Design of Quaternary Logical Circuit Using Voltage and Current Mode Logic

Shweta Hajare and Pravin Dakhole

Research scholar Department of Electronics Engineering,

Yeshwantrao Chavan college of Engg, Nagpur, India

ABSTRACT

In VLSI technology, designers main concentration were on area required and on performance of the device. In VLSI design power consumption is one of the major concerns due to continuous increase in chip density and decline in size of CMOS circuits and frequency at which circuits are operating. By considering these parameter logical circuits are designed using quaternary voltage mode logic and quaternary current mode logic. Power consumption required for quaternary voltage mode logic is 51.78 % less as compared to binary . Area in terms of number of transistor required for quaternary voltage mode logic is 3 times more as compared to binary. As quaternary voltage mode circuit required large area as compared to quaternary current mode circuit but power consumption required in quaternary voltage mode circuit is less than that required in quaternary current mode circuit.

KEYWORDS

Multiple-Valued Logic (MVL), Quaternary voltage mode, Quaternary current mode, MIN, MAX

ORIGINAL SOURCE URL: https://aircconline.com/vlsics/V8N4/8417vlsi01.pdf

http://airccse.org/journal/vlsi/vol8.html

Wednesday, 11 November 2020

Concurrent Ternary Galois-based Computation using Nano-apex Multiplexing Nibs of Regular Three-dimensional Networks, Part I: Basics

Anas N. Al-Rabadi

Department of Computer Engineering, The University of Jordan, Amman – Jordan &

Department of Renewable Energy Engineering, Isra University – Jordan

ABSTRACT

New implementations within concurrent processing using three-dimensional lattice networks via nano carbon-based field emission controlled-switching is introduced in this article. The introduced nano-based three-dimensional networks utilize recent findings in nano-apex field emission to implement the concurrent functionality of lattice networks. The concurrent implementation of ternary Galois functions using nano threedimensional lattice networks is performed by using carbon field-emission switching devices via nano-apex carbon fibers and nanotubes. The presented work in this part of the article presents important basic background and fundamentals with regards to lattice computing and carbon field-emission that will be utilized within the follow-up works in the second and third parts of the article. The introduced nano-based three-dimensional lattice implementations form new and important directions within three-dimensional design in nanotechnologies that require optimal specifications of high regularity, predictable timing, high testability, fault localization, self-repair, minimum size, and minimum power consumption.

KEYWORDS

Carbon nano-apex, Concurrent processing, Field emission, Lattice network, Regularity, Symmetric function.

ORIGINAL SOURCE URL: https://aircconline.com/vlsics/V11N5/11520vlsi01.pdf

http://airccse.org/journal/vlsi/vol11.html

Friday, 6 November 2020

Zigbee Transmitter for IoT Wireless Devices

A.Mounica1 and G.V.Subbareddy2

1MTech VLSI Design, Dept of ECE, GRIET Hyderabad, India.

2Associative Professor in Dept of ECE, GRIET Hyderabad, India.

ABSTRACT

The rapid development in wireless networking has been witnessed in past several years, which aimed on high speed and long range applications. There are different protocol standards used for the short range wireless communication namely the Bluetooth, ZigBee, Wimax and Wi-Fi. Among these standards ZigBee is based on IEEE 802.15.4 protocol can meet a wider variety of real industrial needs due to its long-term battery operation and reliability of the mesh networking architecture. The increasing demand for low data rate and low power networking led to the development of ZigBee technology. This technology was developed for Wireless Personal Area Networks (WPAN), directed at control and military applications, where low cost, low data rate, and more battery life were main requirements. This paper presents VerilogHDL simulation of the Top level module (Cyclic Redundancy Check, Bit-to-Symbol block, Symbol-to-Chip block, OQPSK block and Pulse shaping) of the ZigBee transmitter for IoT applications.

KEYWORDS

Cyclic Redundancy Check, Bit-to-Symbol, Symbol-to-Chip, Offset Quadrature Phase Shift Keying Modulator and Pulse Shaping.

ORIGINAL SOURCE URL: https://aircconline.com/vlsics/V8N5/8517vlsi01.pdf

http://airccse.org/journal/vlsi/vol8.html