DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLER

Smriti Sharma¹ and Balwinder Singh²

^1,2Centre for Development of Advanced Computing, India

ABSTRACT

Memory is an essential part of electronic industry. Since, the processors used in various high performance PCs, network applications and communication equipment require high speed memories. The type of memory used depends on system architecture, and its applications. This paper presents an SRAM architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are inefficient as they require idle cycles when they frequently switch between reading and writing to the memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the basis of area, speed and power.

KEYWORDS ZBT

SRAM, performance analysis, READ/WRITE transitions, speed, area & power

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