DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG TO DIGITAL CONVERTER

Arun Kumar Sunaniya¹ and Kavita Khare²

 Department of Electronics and Communication Engineering MANIT, Bhopal, India

ABSTRACT

This work presents three different approaches which eliminates the resistor ladder completely and hence reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of 0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of 0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 µwatts; Power delay product (PDP) is 415.9 fWs, and the area is 1.89µm2. The second and third approaches are clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 µm2 for Clocked SIS ADC and 107.3 fWs & 1.94 µm2 for Sleep transistor SIS ADC.

KEYWORDS

CMOS 45nm, flash analog to digital converter, low power, resistorless, switched inverter scheme (SIS), sleep transistor.

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics11.pdf

http://airccse.org/journal/vlsi/vol4.html