Low Power Low Voltage Bulk Driven Balanced OTA

Neha Gupta, Sapna Singh, Meenakshi Suthar and Priyanka Soni

Faculty of Engineering Technology, Mody Institute of Technology and Science, Lakshmangarh, Sikar, India

ABSTRACT

The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.

KEYWORDS

Bulk-driven MOS, OTA, BOTA, Body effect

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics11.pdf

https://airccse.org/journal/vlsi/vol2.html

Design and ASIC Implemenatation of DUC/DDC for Communication Systems

Naagesh S. Bhat

Senior Product Engineer, Green Mil International Ltd., Bangalore, India

ABSTRACT

Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a tunable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. Tunable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal’s bandwidth. This also simplifies the complexity of the sampling circuits. Digital Up Conversion (DUC) and Digital Down Conversion (DDC) are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. 

The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and PrimeTime. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and postroute delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock frequency. Both the designs have passed postroute delay based simulations, static performance checks, power domain checks and TSMC’s 65nm design rule checks.

KEYWORDS

Power Line Carrier Communication, Digital Down-Counter, Digital Up-Counter, Application Specific Integrated Circuit, Multi-VDD, TSMC 

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics10.pdf

https://airccse.org/journal/vlsi/vol2.html

An Efficient FPGA Implemenation of MRI Image Filtering and Tumour Characterization Using XILINX System Generator

S. Allin Christe, M. Vignesh and A. Kandaswamy, PSG College of Technology, India

ABSTRACT

This paper presents an efficient architecture for various image filtering algorithms and tumor characterization using Xilinx System Generator (XSG). This architecture offers an alternative through a graphical user interface that combines MATLAB, Simulink and XSG and explores important aspects concerned to hardware implementation. Performance of this architecture implemented in SPARTAN-3E Starter kit (XC3S500E-FG320) exceeds those of similar or greater resources architectures. The proposed architecture reduces the resources available on target device by 50%.

KEYWORDS

MRI, Matlab, Xilinx System Generator, FPGA, Edge Detection

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics09.pdf

https://airccse.org/journal/vlsi/vol2.html

Call for Research Papers! February Issue!

International Journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

http://airccse.org/journal/vlsi/vlsics.html

Submission Deadline : January 08, 2022

Contact Us

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VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology

Ms. Rita M. Shende and Prof. Pritesh R. Gumble

Department of Electronics & Telecommunication, Sipna’s College of Engineering & Technology Amravati, Maharashtra.

Abstract

Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm.

Keyword

ADC, PIPELINE, CMOS 

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics08.pdf

https://airccse.org/journal/vlsi/vol2.html

A Novel Approach to Minimize Spare Cell Leakage Power Consumption During Physical Design Implementation

Vasantha Kumar B.V.P1, Dr. N. S. Murthy Sharma2, Dr. K. Lal Kishore3 and 4Jibanjeet Mishra

1Synopsys (India) Pvt. Ltd, Hyderabad, India.

2Principal, SV Institute of Engineering and Technology, Hyderabad, India.

3JNT University, ECE Dept, Hyderabad

4Synopsys (India) Pvt. Ltd, Hyderabad, India.

ABSTRACT

In IC designs leakage power constitutes significant amount power dissipation because CMOS gates are not perfect switches. The leakage power in CMOS gates is dependent on the states of the inputs. This leakage power will get dissipated even when the gates are in idle conditions. Traditionally ECO cells (or) spare cells remain idle in the design and thus contributes to significant state dependent leakage power consumption. In this paper we proposed novel solution to minimize the state dependent leakage power dissipation of the spare cells.

KEYWORDS

Engineering Change Order (ECO), ECO cell, Spare cell, State dependent, leakage power and switching probability.

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics07.pdf

https://airccse.org/journal/vlsi/vol2.html

Call for Research Papers! December Issue!

International Journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

http://airccse.org/journal/vlsi/vlsics.html

Contact Us

Here's where you can reach us : vlsicsjournal@airccse.org or vlsics@aircconline.com or vlsicsjournal@yahoo.com

Submission Deadline : December 25, 2021

Submission System: http://coneco2009.com/submissions/imagination/home.html

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