POWER EFFICIENT CARRY PROPAGATE ADDER

Laxmi Kumre¹ , Ajay Somkuwar² and Ganga Agnihotri³

^1,2Department of Electronics Engineering, MANIT, Bhopal, INDIA

³Department of Electronics Engineering, MANIT, Bhopal, INDIA

ABSTRACT

Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI technique. GDI technique is power efficient technique for designing digital circuit that consumes less power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum propagation delay, minimum area required and less complexity for designing any digital circuit. We designed Carry Propagate Adder using GDI technique and compared its performance with CMOS technique in terms of area, delay and power dissipation. Circuit designed using CADENCE EDA tool and simulated using SPECTRE VIRTUOSO tool at 0.18m technology. Comparative performance result shows that Carry Propagate Adder using GDI technique dissipated 55.6% less power as compare to Carry Propagate Adder using CMOS technique.

 KEYWORDS

Gate Diffusion Input Technique, Shannon’s Expansion Theorem, Carry Propagate Adder, low power VLSI design.

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics12.pdf

http://airccse.org/journal/vlsi/vol4.html

5^th International Conference on Image and Signal Processing (ISPR -2019) 

December 14~15, 2019, Chennai, India

https://csita2019.org/ispr/index.html

SCOPE

5^th International Conference on Image and Signal Processing (ISPR -2019) is a forum for presenting new advances and research results in the fields of Digital Image Processing. The conference will bring together leading researchers, engineers and scientists in the domain of interest from around the world. The scope of the conference covers all theoretical and practical aspects of the Signal, Image Processing & Pattern Recognition. Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences.

Authors are solicited to contribute to the conference by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the following areas, but are not limited to

TOPICS:

• Image acquisition & Medical Image processing
• Pattern Recognition and Analysis
• Visualization
• Face Recognition & Super-resolution Imaging
• 3D and Stereo Imaging
• Application & Others
• Image Coding and Compression
• Image Segmentation
• Face Recognition
• 3-D and Surface Reconstruction
• Analog and Mixed Signal Processing
• Application & Others
• Applications (Biomedical, Bioinformatics, Genomic, Seismic, Radar, Sonar, Remote Sensing, Positioning, etc.)
• Array Signal Processing
• Audio/Speech Processing and Coding
• Digital & Mobile Signal Processing
• Statistical & Optical Signal Processing
• Data Mining Techniques
• Motion Detection
• Content-based Image retrieval
• Video Signal Processing
• Array Signal Processing
• Audio/Speech Processing and Coding
• Digital & Mobile Signal Processing
• Statistical & Optical Signal Processing
• Constraint Processing
• Distributed Source Coding
• Document Recognition
• DSP Implementation and Embedded Systems
• Face and Gesture
• Hardware Implementation for Signal Processing
• Higher Order Spectral Analysis
• Illumination and Reflectance Modeling
• Image and Video Retrieval
• Image Processing & Understanding
• Image-Based Modeling
• Internet Signal Processing
• Knowledge Representation and High-Level Vision
• Medical Image Analysis
• Multidimensional Signal Processing
• Motion Detection
• Multi-view Geometry
• Data Mining Techniques
• Content-based Image retrieval
• Video Signal Processing
• Watermarking
• Detection and Estimation of Signal Parameters
• Signal Identification
• Nonlinear Signals and Systems
• Time-Frequency Signal Analysis
• Signal Reconstruction
• Spectral Analysis
• Sonar Signal Processing and Localization
• Speech, Audio and Music Processing
• Statistic Learning & Pattern Recognition
• Text processing
• Filter Design and Structures
• FIR, IIR and Adaptive Filters
• Signal Noise Control
• Multiple Filtering and Filter Banks
• Biomedical Imaging Technologies
• Biometrics and Pattern Recognition
• Cognitive and Biologically-inspired Vision
• Color and Texture
• Communication Signal processing
• Computer Communication and Networks
• Computer Vision & VR
• Neural Networks and Genetic Algorithms
• Object Detection, Recognition and Categorization
• Pattern Recognition in New Modalities
• DE for Image Processing
• Performance Evaluation
• Radar Signal Processing
• Remote Sensing
• Segmentation
• Sensor Array and Multi-channel Processing
• Shape Representation
• Signal Processing Education
• Time-Frequency/Time-Scale Analysis
• Video Analysis and Event Recognition
• Video compression & Streaming
• Video Surveillance and Monitoring
• Fuzzy system applications in system and Control Engineering

PAPER SUBMISSION

Authors are invited to submit papers through the Submission System by August 17, 2019. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this conference. The proceedings of the conference will be published by Computer Science Conference Proceedings in Computer Science & Information Technology (CS&IT) series (Confirmed).

 

Selected papers from ISPR -2019, after further revisions, will be published in the special issue of the following journals

• Signal & Image Processing : An In
  
  ternational Journal (SIPIJ)
• International Journal of VLSI Design & Communication Systems (VLSICS)
• International Journal of Embedded Systems and Applications (IJESA)
• The International Journal of Multimedia & Its Applications (IJMA) – ERA Indexed

IMPORTANT DATES

·        Submission Deadline : August 17, 2019

·        Notification                  : October 20, 2019

·        Final Manuscript Due   : November 10, 2019

·        Publication Date          : Determined by the Editor-in-Chief

CONTACT US

Here's where you can reach us: isprconf@yahoo.com or ispr@csita2019.org

SUBMISSION SYSTEM

https://csita2019.org/submission/index.php

DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG TO DIGITAL CONVERTER

Arun Kumar Sunaniya¹ and Kavita Khare²

 Department of Electronics and Communication Engineering MANIT, Bhopal, India

ABSTRACT

This work presents three different approaches which eliminates the resistor ladder completely and hence reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of 0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of 0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 µwatts; Power delay product (PDP) is 415.9 fWs, and the area is 1.89µm2. The second and third approaches are clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 µm2 for Clocked SIS ADC and 107.3 fWs & 1.94 µm2 for Sleep transistor SIS ADC.

KEYWORDS

CMOS 45nm, flash analog to digital converter, low power, resistorless, switched inverter scheme (SIS), sleep transistor.

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics11.pdf

http://airccse.org/journal/vlsi/vol4.html

DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLER

Smriti Sharma¹ and Balwinder Singh²

^1,2Centre for Development of Advanced Computing, India

ABSTRACT

Memory is an essential part of electronic industry. Since, the processors used in various high performance PCs, network applications and communication equipment require high speed memories. The type of memory used depends on system architecture, and its applications. This paper presents an SRAM architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are inefficient as they require idle cycles when they frequently switch between reading and writing to the memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the basis of area, speed and power.

KEYWORDS ZBT

SRAM, performance analysis, READ/WRITE transitions, speed, area & power

Orginal Source URL: http://aircconline.com/vlsics/V4N3/4313vlsics10.pdf

http://airccse.org/journal/vlsi/vol4.html

International Journal of VLSI design & Communication Systems( VLSICS )

http://airccse.org/journal/vlsi/vlsics.html

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

Scope & Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include, but are not limited to, the following:

* Design

* VLSI Circuits

* Computer-Aided Design (CAD)

* Low Power and Power Aware Design

* Testing, Reliability, Fault-Tolerance

* Emerging Technologies

* Post-CMOS VLSI

* VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

* Nano Electronics, Molecular, Biological and Quantum Computing

* Intellectual Property Creating and Sharing

* Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through E-mail; vlsicsjournal@airccse.org.  Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates:

·         Submission Deadline    : August 10, 2019

·         Acceptance Notification :September 10, 2019

·         Final Manuscript Due     : September 18, 2019

·         Publication Date : Determined by the Editor-in-Chief

For other details please visit: http://airccse.org/journal/vlsi/vlsics.html

International Journal of VLSI design & Communication Systems( VLSICS )

http://airccse.org/journal/vlsi/vlsics.html

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

Scope & Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include, but are not limited to, the following:

* Design

* VLSI Circuits

* Computer-Aided Design (CAD)

* Low Power and Power Aware Design

* Testing, Reliability, Fault-Tolerance

* Emerging Technologies

* Post-CMOS VLSI

* VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

* Nano Electronics, Molecular, Biological and Quantum Computing

* Intellectual Property Creating and Sharing

* Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through E-mail; vlsicsjournal@airccse.org.  Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates:

·         Submission Deadline    : August 10, 2019

·         Acceptance Notification :September 10, 2019

·         Final Manuscript Due     : September 18, 2019

·         Publication Date : Determined by the Editor-in-Chief

For other details please visit: http://airccse.org/journal/vlsi/vlsics.html

DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATOR

Jayanthi Vanama and G.L.Sampoorna

Trainee Engineer, Powerwave Technologies Pvt. Ltd., R&D India 

Intern, CONEXANT Systems Pvt. Ltd.

ABSTRACT

A low power programmable low drop-out regulator capable of providing 1V output has been proposed. The regulator requires a supply voltage of 1.2V and works in the temperature range of -40 to 125 ˚C in nominal corner (i.e, normal doping for PMOS and NMOS Field Effect Transistors), yielding a load regulation of 3%. The output voltage level is controlled externally by means of 2 1-bit control signals. The circuit provides a DC gain of 30 dB and a maximum DC Power Supply Rejection Ratio of -35 dB and a worst case PSRR of -20 dB. Power dissipation in the load is nearly 100 µW.

KEYWORDS

Low Drop-Out, Voltage Regulator, Low Power, Low quiescent current.

Orginal Sourcr URL: http://aircconline.com/vlsics/V4N3/4313vlsics09.pdf

http://airccse.org/journal/vlsi/vol4.html