DESIGN AND PERFORMANCE ANALYSIS OF VARIOUS ADDERS AND MULTIPLIERS USING GDI TECHNIQUE

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International Journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

Webpage URL : http://airccse.org/journal/vlsi/vlsics.html

DESIGN AND PERFORMANCE ANALYSIS OF VARIOUS ADDERS AND MULTIPLIERS USING GDI TECHNIQUE

Simran kaur, Balwinder Singh and D.K Jain 

ABSTRACT

With the active development of portable electronic devices, the need for low power dissipation, high speed and compact implementation, give rise to several research intentions. There are several design techniques used for the circuit configuration in VLSI systems but there are very few design techniques that gives the required extensibility. This paper describes the implementation of various adders and multipliers. The design approach proposed in the article is based on the GDI (Gate Diffusion Input) technique. The paper also includes a comparative analysis of this low power method over CMOS design style with respect to power consumption, area complexity and delay. In this paper, a new GDI based cell designs are projected and are found to be efficient in terms of power consumption and area in comparison with existing CMOS based cell functionality. Power and delay has been calculated using Cadence Virtuoso tool at 45nm CMOS technology. The results obtained show better power and delay performance of the proposed designs at 1.3V supply voltage.

KEYWORDS

CMOS, GDI, Adders, Low Power, Digital Design

Full Text URL : https://aircconline.com/vlsics/V6N5/6515vlsi04.pdf