Test Generation for Analog and Mixed-Signal Circuits Using Hybrid System Models

Tarik NAHHAL1 and Thao Dang2, 1Hassan II University, Morocco and 2VERIMAG, France

ABSTRACT

In this paper we propose an approach for testing time-domain properties of analog and mixed-signal circuits. The approach is based on an adaptation of a recently developed test generation technique for hybrid systems and a new concept of coverage for such systems. The approach is illustrated by its application to some benchmark circuits.

KEYWORDS

Hybrid System, Formal Methods in Conformance Testing, Analog and Mixed-Signal Circuit. 

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics02.pdf

https://airccse.org/journal/vlsi/vol2.html

#research #VLSI #Embeddedsystem #Electronics #CMOSTechnologies

A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

Mouna Karmani*, Chiraz Khedhiri*, Belgacem Hamdi* & Brahim Bensalem**

*Electronics and Microelectronics Laboratory, Monastir, Tunisia

**Embedded and Communication Group, Intel Corporation, Chandler, AZ, USA

Abstract:

In this paper, we propose a simulation-before-test (SBT) fault diagnosis methodology based on the use of a fault dictionary approach. This technique allows the detection and localization of the most likely defects of open-circuit type occurring in Complementary Metal–Oxide–Semiconductor (CMOS) analog integrated circuits (ICs) interconnects. The fault dictionary is built by simulating the most likely defects causing the faults to be detected at the layout level. Then, for each injected fault, the spectre’s frequency responses and the power consumption obtained by simulation are stored in a table which constitutes the fault dictionary. In fact, each line in the fault dictionary constitutes a fault signature used to identify and locate a considered defect. When testing, the circuit under test is excited with the same stimulus, and the responses obtained are compared to the stored ones. To prove the efficiency of the proposed technique, a full custom CMOS operational amplifier is implemented in 0.25 µm technology and the most likely faults of opencircuit type are deliberately injected and simulated at the layout level.

Keywords:

Analog testing, fault diagnosis, fault dictionary, Fast Fourier Transform (FFT), power consumption, opencircuit fault. 

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics01.pdf

https://airccse.org/journal/vlsi/vol2.html

Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Utilization

Bhavana Pote1,V. N. Nitnaware1 and S. S. Limaye2, 1Ramdeobaba Kamla Nehru College of Engg, India and 2Jhulelal Institute of Technology, India

Abstract:

With the shrinking technology, reduced scale and power-hungry chip IO leads to System on Chip. The design of SOC using traditional standard bus scheme encounters with issues like non-uniform delay and routing problems. Crossbars could scale better when compared to buses but tend to become huge with increasing number of nodes. NOC has become the design paradigm for SOC design for its highly regularized interconnect structure, good scalability and linear design effort. The main components of an NoC topology are the network adapters, routing nodes, and network interconnect links. This paper mainly deals with the implementation of full custom SRAM based arrays over D FF based register arrays in the design of input module of routing node in 2D mesh NOC topology. The custom SRAM blocks replace DFF(D flip flop) memory implementations to optimize area and power of the input block. Full custom design of SRAMs has been carried out by MILKYWAY, while physical implementation of the input module with SRAMs has been carried out by IC Compiler of SYNOPSYS.The improved design occupies approximately 30% of the area of the original design. This is in conformity to the ratio of the area of an SRAM cell to the area of a D flip flop, which is approximately 6:28.The power consumption is almost halved to 1.5 mW. Maximum operating frequency is improved from 50 MHz to 200 MHz. It is intended to study and quantify the behavior of the single packet array design in relation to the multiple packet array design. Intuitively, a common packet buffer would result in better utilization of available buffer space. This in turn would translate into lower delays in transmission. A MATLAB model is used to show quantitatively how performance is improved in a common packet array design.

Keywords : 2D mesh, virtual output queuing, HOL blocking, FIFO, DDC file, GDS format. 

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics15.pdf

https://airccse.org/journal/vlsi/vol2.html

Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Technology

Rajendra Prasad S1, B K Madhavi2 and K Lal Kishore3, 1ACE Engineering College, India, 2GCET, India and 3JNT University, India

ABSTRACT

The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.

KEYWORDS

SRAM Cell, CNTFET, 32nm Technology, HSPICE, Low-Power

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics14.pdf

https://airccse.org/journal/vlsi/vol2.html