A New Full Adder Cell for Molecular Electronics

Mehdi Ghasemi1,2, Mohammad Hossein Moaiyeri1,2, and Keivan Navi1,2

1Faculty of Electrical and Computer Engineering, Shahid Beheshti University G.C., Tehran, Iran.

2Nanotechnology and Quantum Computing Lab, Shahid Beheshti University G.C., Tehran, Iran.

ABSTRACT

Due to high power consumption and difficulties with minimizing the CMOS transistor size, molecular electronics has been introduced as an emerging technology. Further, there have been noticeable advances in fabrication of molecular wires and switches and also molecular diodes can be used for designing different logic circuits. Considering this novel technology, we use molecules as the active components of the circuit, for transporting electric charge. In this paper, a full adder cell based on molecular electronics is presented. This full adder is consisted of resonant tunneling diodes and transistors which are implemented via molecular electronics. The area occupied by this kind of full adder would be much times smaller than the conventional designs and it can be used as the building block of more complex molecular arithmetic circuits.

KEYWORDS

Logic circuits, full adder, nanotechnology, molecular electronics, resonant tunneling diode (RTD)

Original Source URL: https://aircconline.com/vlsics/V2N4/2411vlsics01.pdf

https://airccse.org/journal/vlsi/vol2.html

Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Universal Logic Gates

K. Ragini1, M. Satyam2 and B. C. Jinaga3 , 1G. Narayanamma Institute of Technology & Science, India, 2International Institute of Information Technology, India and 3Jawaharlal Nehru Technology University, India

ABSTRACT

In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages. 

The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..

The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.

KEYWORDS

Sub- threshold, Dynamic threshold MOS Inverter, Propagation delay, Noise-margin, Variable threshold MOS Inverter, Power dissipation.

Original Source URL: https://aircconline.com/vlsics/V1N1/0310vlsics4.pdf

https://airccse.org/journal/vlsi/vol1.html

Arithmetic Operations in Multi-Valued Logic

Vasundara Patel K. S1 and K. S Gurumurthy2, 

1Vishweshwaraiah Technological University, India and 2UVCE, Bangalore, India

Abstract

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.

KEYWORDS

Multiple-valued logic, Quaternary logic, Modulo-n addition and multiplication, Galois addition and multiplication.

Original Source URL: https://aircconline.com/vlsics/V1N1/0310vlsics3.pdf

https://airccse.org/journal/vlsi/vol1.html