Wednesday, 31 March 2021

A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing for Wireless Applications

 S. L. Haridas1 and Dr. N. K. Choudhari2 

1Prof. & Head of E&T Engg., B. D. College of Engg., Sevagram (M.S.), India

 2Principal, Smt. Bhagvati Chaturvedi College of Engg., Nagpur (M.S.), India

 ABSTRACT 

This work proposes the low power implementation of Viterbi Decoder. Majority of viterbi decoder designs in the past use simple Register Exchange or Traceback method to achieve very high speed and low power decoding respectively, but it suffers from both complex routing and high switching activity. Here simplification is made in survivor memory unit by storing only m-1 bits to identify previous state in the survivor path, and by assigning m-1 registers to decision vectors. This approach eliminates unnecessary shift operations. Also for storing the decoded data only half memory is required than register exchange method. In this paper Hybrid approach that combines both Traceback and Register Exchange schemes has been applied to the viterbi decoder design. By using distance properties of encoder we further modified to minimum transition hybrid register exchange method. It leads to lower dynamic power consumption because of lower switching activity. Dynamic power estimation obtained through gate level simulation indicates that the proposed design reduces the power dissipation of a conventional viterbi decoder design by 30%. 

 KEYWORDS 

Traceback method, Register Exchange method, Hybrid Register Exchange method, Minimum Transition Register Exchange Method. 

 Original Source URL: https://aircconline.com/vlsics/V1N4/1210vlsics02.pdf 

http://airccse.org/journal/vlsi/vol1.html






Wednesday, 24 March 2021

A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register (MISR)

Afaq Ahmad

Department of Electrical and Computer Engineering College of Engineering, Sultan Qaboos University P. O. Box 33, Postal Code 123; Muscat, Sultanate of Oman

ABSTRACT

This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (Multi-Input Shift Register), used in an LFSR based digital circuit testing technique. The investigation is carried-out through an extensive simulation study of the effectiveness of the LFSR based digital circuit testing technique. The results of the study show that when the identical characteristic polynomials of order n are used in both pseudo-random test-pattern generator, as well as in Multi-Input Shift Register (MISR) signature analyzer (parallel type) then the probability of aliasing errors remains unchanged due to the changes in the initial loadings of the pseudo-random test-pattern generator.

KEYWORDS

LFSR, MISR, BIST, Characteristic Polynomial, Primitive

Original Source URL: https://aircconline.com/vlsics/V1N4/1210vlsics01.pdf

http://airccse.org/journal/vlsi/vol1.html




Monday, 15 March 2021

March 2021: Top Read Articles in VLSI design & Communication Systems

International Journal of VLSI design & Communication Systems ( VLSICS ) 

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

http://airccse.org/journal/vlsi/vlsics.html

#CMOS #vlsicircuits

Submission Deadline: March 20, 2021

Contact Us

Here's where you can reach us: vlsicsjournal@airccse.org or vlsicsjournal@yahoo.com

Academia Link: https://www.academia.edu/45530437/March_2021_Top_Read_Articles_in_VLSI_design_and_Communication_Systems


Wednesday, 10 March 2021