International Journal Of VLSI Design & Communication Systems ( VLSICS )

Saturday, 20 February 2021

8th International Conference on Signal, Image Processing and Multimedia (SPM 2021)

September 25 ~ 26, 2021, Toronto, Canada

https://cseit2021.org/spm/index

#signalprocessing #imageprocessing

Submission Deadline: February 27, 2021

Here's where you can reach us : spm@cseit2021.org or spmconf@yahoo.com

Submission system

https://cseit2021.org/submission/index.php

Wednesday, 17 February 2021

Design And Implementation of Combined Pipelining and Parallel Processing Architecture for FIR and IIR Filters Using VHDL

Jacinta Potsangbam1 and Manoj Kumar2

1M. Tech VLSI Design, Dept. of ECE, National Institute of Technology, Manipur, India

2Assistant Professor, Dept. of ECE, National Institute of Technology, Manipur, India

ABSTRACT

Along with the advancement in VLSI (Very Large Scale Integration) technology, the implementation of Finite impulse response (FIR) filters and Infinite impulse response (IIR) filters with enhanced speed has become more demanding. This paper aims at designing and implementing a combined pipelining and parallel processing architecture for FIR and IIR filter using VHDL (Very High Speed Integrated Circuit Hardware Descriptive Language) to reduce the power consumption and delay of the filter. The proposed architecture is compared with the original FIR and IIR filter respectively in terms of speed, area, and power. Also, the proposed architecture is compared with existing architectures in terms of delay. The implementation is done by using VHDL codes. FIR and IIR filters structures are implemented at 1200 KHz clock frequency. Synthesis and simulation have been accomplished on Artix-7 series FPGA, target device (xc7a200tfbg676) (speed grade -1) using VIVADO 2016.3.

KEYWORDS

DSP, FIR, FPGA, IIR, MIMO.

Original Source URL: https://aircconline.com/vlsics/V10N4/10419vlsi01.pdf

http://airccse.org/journal/vlsi/vol10.html

Monday, 8 February 2021

Friday, 5 February 2021

Duty Cycle Corrector Using Pulse Width Modulation

Meghana Patil1, Dr. Kiran Bailey2 and Rajanikanth Anuvanahally3

1Department of Electronics and Communication, BMSCE, Bengaluru, Karnataka, India

2Department of Electronics and Communication, BMSCE, Bengaluru, Karnataka, India

3Senior Member IEEE, Bengaluru, Karnataka, India

ABSTRACT

In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW.

KEYWORDS

DCC, Integrator, Control voltage generator, frequency range

ORIGINAL SOURCE URL: https://aircconline.com/vlsics/V10N3/10319vlsi01.pdf

http://airccse.org/journal/vlsi/vol10.html