9th International Conference on Digital Image Processing and Pattern Recognition (DPPR 2019)

December 21~22, 2019, Sydney, Australia

https://cndc2019.org/dppr/index.html

Venue : Werrington Park Corporate Centre, Sydney, Australia

Contact Us

Here's where you can reach us : dppr@cndc2019.org or dpprc@yahoo.com

Most Viewed Current Issue Paper for VLSICS in Acadamia

International journal of VLSI design & Communication Systems ( VLSICS )

http://airccse.org/journal/vlsi/vlsics.html

ISSN : 0976 - 1357 (Online); 0976 - 1527(print)  

EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON FPGA

http://aircconline.com/vlsics/V10N2/10219vlsi01.pdf

https://www.academia.edu/40381650/EFFICIENT_ABSOLUTE_DIFFERENCE_CIRCUIT_FOR_SAD_COMPUTATION_ON_FPGA

https://www.academia.edu/40546787/Most_Viewed_Current_Issue_Paper_for_VLSICS

Most Trending Article In Acadamia

International journal of VLSI design & Communication Systems  ( VLSICS )

http://airccse.org/journal/vlsi/vlsics.html

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

VLSI DESIGN OF AMBA BASED AHB2APB BRIDGE

http://aircconline.com/vlsics/V9N3/9318vlsi02.pdf

https://www.academia.edu/36956498/VLSI_DESIGN_OF_AMBA_BASED_AHB2APB_BRIDGE

Welcome to SPM 2019

6th International Conference on Signal, Image Processing and Multimedia

November 23 ~ 24, 2019, Zurich, Switzerland

https://cseit2019.org/spm/index.html

Submission Deadline :October 05, 2019

Here's where you can reach us : spm@cseit2019.org (or) spmconf@yahoo.com

Submission Link :http://cseit2019.org/submission/index.php

EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON FPGA

Jaya Koshta, Kavita Khare and M.K Gupta

Maulana Azad National Institute of Technology, Bhopal

ABSTRACT

Video Compression is very essential to meet the technological demands such as low power, less memory and fast transfer rate for different range of devices and for various multimedia applications. Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder which contributes to significant compression gain.Sum of Absolute Difference (SAD) is used as distortion metric in ME process.In this paper, efficient Absolute Difference(AD)circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based on modified 1’s complement principle and conditional sum adder scheme. Results shows that proposed architecture reduces delay by 15% and number of slice LUTs by 42 % as compared to conventional architecture. Simulation and synthesis are done on Xilinx ISE 14.2 using Virtex 7 FPGA.

 KEYWORDS

HEVC, motion estimation, sum of absolute difference, parallel prefix adders, Brent Kung Adder.

Orginal Source URL: http://aircconline.com/vlsics/V10N2/10219vlsi01.pdf

http://airccse.org/journal/vlsi/vol10.html

Trending paper on academia!

International journal of VLSI design & Communication Systems  ( VLSICS )

http://airccse.org/journal/vlsi/vlsics.html

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM

http://aircconline.com/vlsics/V9N3/9318vlsi03.pdf

https://www.academia.edu/36956674/VERIFICATION_OF_DRIVER_LOGIC_USING_AMBA-_AXI_UVM

10th International Conference on VLSI (VLSI 2019)

December 21~22, 2019, Sydney, Australia

https://cndc2019.org/vlsi/index.html

Paper Submission : http://cndc2019.org/submission/index.php

Contact Us :  vlsi@cndc2019.org