Design and Implementation of FPGA Based Signal Processing Card

Priya Gupta1 and Deepak Gupta2,1Banasthali University, India and 2Alpine System, India

ABSTRACT

This paper describes the design of FPGA based signal processing card. An on board real time digital signal processing system is designed using FPGA. The platform can decode process of various kinds of digital and analog signals simultaneously. The design trend in this card is towards small size, high integration and fast real time processing. For the optimum performance a 16 bit 1 MSPS ADC is used which is interfaced with FPGA to make all the data processing onboard in real time. This card can be used in many signal processing based applications like audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications by interfacing several separate board using inbuilt I/O’s, each with a number of input channels that will communicate with each other in real time over a high speed communication link. The resulting images can be displayed directly on LCD or OLED panel displays using I/O’s peripherals. The project introduces many challenging issues, which are being addressed in turn with different prototype designs. These issues are the ADC performance, interfacing the ADCs to the FPGA, implementing the flexible processing algorithms and high speed interconnection between the boards. 

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics11.pdf

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Submission Deadline : July 02, 2022

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International Journal of VLSI design & Communication Systems (VLSICS)

 International Journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

https://airccse.org/journal/vlsi/vlsics.html

June 2022: Top 10 Read Articles in VLSI design & Communication Systems

https://www.academia.edu/82092399/June_2022_Top_10_Read_Articles_in_VLSI_design_and_Communication_Systems

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Submission Deadline : June 25, 2022

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#VHDL #VLSI #integratedcircuit #microelectronics #CMOS #medicalelectronics #microprocessors #microcontrollers #opamp

International Journal of VLSI design & Communication Systems (VLSICS)

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

https://airccse.org/journal/vlsi/vlsics.html

Indexing URL: https://airccse.org/journal/vlsi/indexing.html

Submission Deadline: June 25, 2022

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Performance analysis of DWT based OFDM over FFT based OFDM and implementing on FPGA

Veena M. B and M. N. Shanmukha Swamy, SJCE, India

ABSTRACT

Growth in technology has led to unprecedented demand for high speed architectures for complex signal processing applications. In 4G wireless communication systems, bandwidth is a precious commodity, and service providers are continuously met with the challenge of accommodating more users with in a limited allocated bandwidth. To increase data rate of wireless medium with higher performance, OFDM (orthogonal frequency division multiplexing) is used. Recently DWT (Discrete wavelet transforms) is adopted in place of FFT (Fast Fourier transform) for frequency translation. Modulation schemes such as 16-QAM, 32-QAM, 64-QAM and 128-QAM (Quadrature amplitude modulation) have been used in the developed OFDM system for both DWT and FFT based model. In this paper we propose a DWT-IDWT based OFDM transmitter and receiver that achieve better performance in terms SNR and BER for AWGN channel. It proves all the wavelet families better over the IFFT-FFT implementation. The OFDM model is developed using Simulink, various test cases have been considered to verify its performance. The DWTOFDM using Lifting Scheme architecture is implemented on FPGA optimizing hardware, speed & cost. The wavelet filter used for this is Daubechies (9, 7) with N=2. The RTL code is written in Verilog-HDL and simulated in Modelsim. The design is then synthesized in Xilinx and implemented on Virtex5 FPGA board and the results were validated using ChipScope.

Keywords: 

FFT, DWT, OFDM, BER, Lifting scheme, Simulink

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics10.pdf

https://airccse.org/journal/vlsi/vol2.html

Area-Efficient Design of Scheduler for Routing Node of Network-On-Chip

Rehan Maroofi1,V. N. Nitnaware1 and S. S. Limaye2,1Ramdeobaba Kamla Nehru College of Engg, India and 2Jhulelal Institute of Technology, India

ABSTRACT

Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.

KEYWORDS

Network-on-Chip, System-on-Chip, On-chip routing switch, Scheduler, iSLIP, Synthesis.

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics09.pdf

https://airccse.org/journal/vlsi/vol2.html

International Journal of VLSI design & Communication Systems (VLSICS)

 ISSN: 0976 - 1357 (Online); 0976 - 1527(print) 

http://airccse.org/journal/vlsi/vlsics.html

 

Scope & Topics 

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.

 

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications. 

Topics of interest include, but are not limited to, the following: 

*  Design

*  VLSI Circuits

*  Computer-Aided Design (CAD)

*  Low Power and Power Aware Design

*  Testing, Reliability, Fault-Tolerance

*  Emerging Technologies

*  Post-CMOS VLSI

*  VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

*  Nano Electronics, Molecular, Biological and Quantum Computing

*  Intellectual Property Creating and Sharing

*  Wireless Communications 

Paper Submission 

Authors are invited to submit papers for this journal through E-Mail: vlsics@aircconline.com or through Submission System. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal. 

Important Dates: 

• Submission Deadline : February 04, 2023
• Notification                   : February 25, 2023
• Final Manuscript Due : February 27, 2023

·         Publication Date          : Determined by the Editor-in-Chief 

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Pipelined Architecture of 2D-DCT, Quantization and ZigZag Process for JPEG Image Compression Using VHDL

T. Pradeepthi and Addanki Purna Ramesh, Sri Vasavi Engg College, India

ABSTRACT

This paper presents the architecture and VHDL design of a Two Dimensional Discrete Cosine Transform (2D-DCT) with Quantization and zigzag arrangement. This architecture is used as the core and path in JPEG image compression hardware. The 2D- DCT calculation is made using the 2D- DCT Separability property, such that the whole architecture is divided into two 1D-DCT calculations by using a transpose buffer. Architecture for Quantization and zigzag process is also described in this paper. The quantization process is done using division operation. This design aimed to be implemented in Spartan-3E XC3S500 FPGA. The 2D- DCT architecture uses 1891 Slices, 51I/O pins, and 8 multipliers of one Xilinx Spartan-3E XC3S500E FPGA reaches an operating frequency of 101.35 MHz One input block with 8 x 8 elements of 8 bits each is processed in 6604 ns and pipeline latency is 140 clock cycles.

KEYWORDS

JPEG, discrete cosine transform (DCT), quantization, zigzag, FPGA

Original Source URL: https://aircconline.com/vlsics/V2N3/2311vlsics08.pdf

https://airccse.org/journal/vlsi/vol2.html