Low Power Reversible Parallel Binary Adder/Subtractor

Rangaraju H G1, Venugopal U2, Muralidhara K N3, Raja K B2

1Department of Telecommunication Engineering, Bangalore Institute of Technology, Bangalore, India

2Department of Electronics and Communication Engineering, University Visvesvaraya College of Engineering, Bangalore, India

3Department of Electronics and Communication Engineering, P E S College of Engineering, Mandya, Karnataka, India

Abstract

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.

Keywords

Reversible Logic, Garbage Input/output, Quantum Cost, Low Power, Reversible Parallel Binary Adder/Subtractor.

Original Source URL: https://aircconline.com/vlsics/V1N3/0910vlsics03.pdf

http://airccse.org/journal/vlsi/vol1.html

Heuristic approach to optimize the number of test cases for simple circuits

SM. Thamarai1, K.Kuppusamy2 and T. Meyyappan3

1Research scholar, 2Associate Professor&Research Supervisor, 3Associate Professor

Department of Computer Science and Engineering, Alagappa University, Karaikudi-630003, Tamilnadu, South India.

ABSTRACT

In this paper a new solution is proposed for testing simple stwo stage electronic circuits. It minimizes the number of tests to be performed to determine the genuinity of the circuit. The main idea behind the present research work is to identify the maximum number of indistinguishable faults present in the given circuit and minimize the number of test cases based on the number of faults that has been detected. Heuristic approach is used for test minimization part, which identifies the essential tests from overall test cases. From the results it is observed that, test minimization varies from 50% to 99% with the lowest one corresponding to a circuit with four gates .Test minimization is low in case of circuits with lesser input leads in gates compared to greater input leads in gates for the boolean expression with same number of symbols. Achievement of 99% reduction is due to the fact that the large number of tests find the same faults. The new approach is implemented for simple circuits. The results show potential for both smaller test sets and lower cpu times.

KEYWORDS

Adaptive Scheduled Fault Detection, CombinationalCircuits, Fault Library, Heuristic Approach , Test Minimization. 

Original Source URL: https://aircconline.com/vlsics/V1N3/0910vlsics02.pdf

http://airccse.org/journal/vlsi/vol1.html

A High-Swing OTA with wide Linearity for design of self-tunable linear resistor

Nikhil Raj, R.K.Sharma

Department of Electronics and Communication Engineering, National Institute of Technology, Kurukshetra Haryana, 136119, India

ABSTRACT

Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.

KEYWORDS

Bulk-input, Wilson mirror, Linear range, MOS resistor

Original Source URL: https://aircconline.com/vlsics/V1N3/0910vlsics01.pdf

http://airccse.org/journal/vlsi/vol1.html