Efficient Absolute Difference Circuit for SAD Computation On FPGA

Jaya Koshta, Kavita Khare and M.K Gupta

Maulana Azad National Institute of Technology, Bhopal

ABSTRACT

Video Compression is very essential to meet the technological demands such as low power, less memory and fast transfer rate for different range of devices and for various multimedia applications. Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder which contributes to significant compression gain.Sum of Absolute Difference (SAD) is used as distortion metric in ME process.In this paper, efficient Absolute Difference(AD)circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based on modified 1’s complement principle and conditional sum adder scheme. Results shows that proposed architecture reduces delay by 15% and number of slice LUTs by 42% as compared to conventional architecture. Simulation and synthesis are done on Xilinx ISE 14.2 using Virtex 7 FPGA.

KEYWORDS

HEVC, motion estimation, sum of absolute difference, parallel prefix adders, Brent Kung Adder.

ORIGINAL SOURCE URL: https://aircconline.com/vlsics/V10N2/10219vlsi01.pdf

http://airccse.org/journal/vlsi/vol10.html

A Methodology for Improvement of Roba Multiplier for Electronic Applications

1Angila Rose Daniel and 2B. Deepa

1M.Tech in VLSI and embedded systems, Kerala technical university, India

2Assistant professor, EC Department, Kerala technical university, India

ABSTRACT

In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to around the operands to the closest exponent of 2. This way the machine intensive a part of the multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is evaluated by comparing its performance with those of some approximate and correct multipliers using different design parameters. In this proposed approach combined the conventional RoBA multiplier with Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the DSP.

KEYWORDS

Accuracy, approximate computing, efficient, error analysis, high speed multiplier, RoBa architecture, kogge stone adder, DSP processing

ORIGINAL SOURCE URL: https://aircconline.com/vlsics/V10N1/10119vlsi01.pdf

http://airccse.org/journal/vlsi/vol10.html

Call for Papers - International Journal of VLSI design & Communication Systems ( VLSICS )

 

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

 

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Scope & Topics

 

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas. 

 

Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

 

Topics of interest include, but are not limited to, the following: 

 

* Design

* VLSI Circuits

* Computer-Aided Design (CAD)

* Low Power and Power Aware Design

* Testing, Reliability, Fault-Tolerance

* Emerging Technologies

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* VLSI Applications (Communications, Video, Security, Sensor Networks, etc)

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Paper Submission 

 

Authors are invited to submit papers for this journal through E-Mail: vlsicsjournal@airccse.org or through Submission System. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

 

Important Dates:

 

·         Submission Deadline : December 26, 2020

·         Notification                   : January 26, 2021

·         Final Manuscript Due   :   February 03, 2021

·         Publication Date          : Determined by the Editor-in-Chief 

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Concurrent Ternary Galois-based Computation using Nano-apex Multiplexing Nibs of Regular Three-dimensional Networks, Part I: Basics

 International Journal of VLSI design & Communication Systems ( VLSICS ) 

ISSN: 0976 - 1357 (Online); 0976 - 1527(print)

http://airccse.org/journal/vlsi/vlsics.html

Concurrent Ternary Galois-based Computation using Nano-apex Multiplexing Nibs of Regular Three-dimensional Networks, Part I: Basics

Anas N. Al-Rabadi

Department of Computer Engineering, The University of Jordan, Amman – Jordan &

Department of Renewable Energy Engineering, Isra University – Jordan

ORIGINAL SOURCE URL: https://aircconline.com/vlsics/V11N5/11520vlsi01.pdf

http://airccse.org/journal/vlsi/vol11.html

Here's where you can reach us : vlsicsjournal@airccse.org or vlsicsjournal@yahoo.com

Top Read Articles in VLSI design & Communication Systems!

VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM

Bijal Thakkar1and V Jayashree2

1Research Scholar, Electronics Dept., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji, Maharashtra, India. 2Professor, Electronics Dept ., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji, Maharashtra, India.

ABSTRACT

Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of its high performance and high-frequency operation without using complex bridges. AXI is also backwardcompatible with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the other protocol but it is possible in AXI because it contains different write address and data channels and AXI also supports out of order transfer based on the transaction ID which is generated at the start of the transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification Methodology (UVM).The signaling of the five channels such as write address, write data, write response, read address, read data channel of AXI protocol are considered for verification. According to the AXI protocol,the signals of these channels are driven to the interconnect and results are observed for single master and single slave. The driver logic has been implemented and verified successfully according to AXI protocol using the Rivera Pro. The results observed for single master and single slave have shown the correctness of AMBA-AXI design in Verilog.

KEYWORDS

AMBA(Advance Microcontroller Bus Architecture),AXI(Advanced Extensible Interface),UVM(Universal Verification Methodology),channel.

For More Details :

https://aircconline.com/vlsics/V9N3/9318vlsi03.pdf

https://www.cseij.org/topcited/topreadarticlesinVLSIdesign&communicationsystems.html